multipdp8 - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Only sample RS232 signals once per clock; use a delayed flop internally.	Julian Blake Kongslie	2022-05-22	1	-9/+19
\| \| \| \|	This removes metastability issues on inputs and makes everything work.
*	Fix the RS232 receive state machine 😠💢:mad:	Julian Blake Kongslie	2022-05-15	1	-1/+1
\| \| \| \| \| \| \| \| \|	Our current consensus is that we have a bug which causes the RX state machine to make incomprehensible jumps when the sample counter is more than about 9 bits wide. We haven't completely pinned down the problem; we saw it when running at 1Mbaud with a 7 bit (one extra bit) counter. I hate Verilog and Altera, both exclusively and in combination.
*	Only phase shift the RS232 tx clock when we are between bytes.	Julian Blake Kongslie	2022-05-15	1	-1/+17
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*	Consistent RS232 wire names (DCE side names is used everywhere)	Julian Blake Kongslie	2022-05-15	1	-27/+27
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*	Demand that CTS is asserted for multiple symbol periods before transmit.	Julian Blake Kongslie	2022-05-08	1	-1/+8
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*	Proper serial port for memory downloads. 115200 8O2 RS232 with CRTRTS.	Julian Blake Kongslie	2022-05-08	1	-33/+76
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*	Oversample RS232 RX uart.	Julian Blake Kongslie	2022-04-22	1	-30/+49
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*	Asynchronous reset on RS232 uart.	Julian Blake Kongslie	2022-04-22	1	-2/+2
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*	Transmit and receive an even parity bit in RS232 uart.	Julian Blake Kongslie	2022-04-22	1	-0/+23
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*	Transmit two stop bits to RS232 uart.	Julian Blake Kongslie	2022-04-22	1	-2/+8
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*	Working (but very slow) RS232 UART	Julian Blake Kongslie	2022-04-17	1	-12/+14
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*	First pass at RS232 tx/rx modules.	Julian Blake Kongslie	2022-03-27	1	-0/+131