multipdp8 - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Collapse)	Author	Age	Files	Lines
*	Proper serial port for memory downloads. 115200 8O2 RS232 with CRTRTS.	Julian Blake Kongslie	2022-05-08	1	-61/+57
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*	Oversample RS232 RX uart.	Julian Blake Kongslie	2022-04-22	1	-12/+28
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*	Working (but very slow) RS232 UART	Julian Blake Kongslie	2022-04-17	1	-1/+132
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*	Use the DF and IF switches as a selector for which PDP-8 owns the panel.	Julian Blake Kongslie	2022-03-27	1	-89/+92
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*	Add a clock output pin for debugging the PLL.	Julian Blake Kongslie	2022-03-27	1	-0/+3
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*	Reduce internal clock speed to 30MHz.	Julian Blake Kongslie	2022-03-27	1	-2/+2
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*	Run ~EIGHT GODDAMN PDP-8s IN PARALLEL~	Julian Blake Kongslie	2022-03-20	1	-41/+113
\| \| \| \| \| \|	It looks like we could probably fit 16 on the current FPGA, just about. (doesn't meet timing at 50MHz, should in theory work at 40MHz)
*	Add memory arbiter and broadcast in between command UART and DRAM.	Julian Blake Kongslie	2022-03-13	1	-17/+63
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*	Change FIFO size for UARTs to 1024 bytes in each direction.	Julian Blake Kongslie	2022-03-13	1	-2/+2
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*	Initial commit.	Julian Blake Kongslie	2022-02-27	1	-0/+298