| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Reduce internal clock speed to 30MHz. | Julian Blake Kongslie | 2022-03-27 | 1 | -2/+2 |
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| * | Run ~*EIGHT GODDAMN PDP-8s IN PARALLEL*~ | Julian Blake Kongslie | 2022-03-20 | 1 | -41/+113 |
| | | | | | | | It looks like we could probably fit 16 on the current FPGA, just about. (doesn't meet timing at 50MHz, should in theory work at 40MHz) | ||||
| * | Add memory arbiter and broadcast in between command UART and DRAM. | Julian Blake Kongslie | 2022-03-13 | 1 | -17/+63 |
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| * | Change FIFO size for UARTs to 1024 bytes in each direction. | Julian Blake Kongslie | 2022-03-13 | 1 | -2/+2 |
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| * | Initial commit. | Julian Blake Kongslie | 2022-02-27 | 1 | -0/+298 |
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index : multipdp8 | |
| Unnamed repository; edit this file 'description' to name the repository. | Julian Blake Kongslie |
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