From 3e5a998a2cb380d90615b524b5e41c671ab8004d Mon Sep 17 00:00:00 2001 From: Julian Blake Kongslie Date: Sun, 29 May 2022 16:38:00 -0700 Subject: Add support for bulk memory dumping to command parser. --- hdl/command_parser.sv | 67 ++++++++++++++++++++++++++++++++++----------------- hdl/result_printer.sv | 37 +++++++++++++++++++++------- hdl/top.sv | 12 +++++++++ 3 files changed, 85 insertions(+), 31 deletions(-) diff --git a/hdl/command_parser.sv b/hdl/command_parser.sv index 964ac12..1520db4 100644 --- a/hdl/command_parser.sv +++ b/hdl/command_parser.sv @@ -16,19 +16,23 @@ module command_parser , input bit command_ready , output bit command_valid , output ram_command_t command_data + + , input bit loop_ready + , output bit loop_valid + , output bit loop_data ); bit input_byte_valid; uart_byte_t input_byte; - bit [`RAM_ADDRESS_BITS:0] zero_count; + bit [`RAM_ADDRESS_BITS:0] loop_count; (* syn_encoding = "one-hot" *) enum int unsigned { READ_COMMAND , READ_ADDRESS , READ_DATA - , READ_ZERO_COUNT - , ZERO_MEMORY + , READ_LOOP_COUNT + , LOOP_MEMORY } state; always @(posedge clock) begin @@ -38,9 +42,10 @@ module command_parser for (int i = 0; i < `RAM_LINE_WORDS; i = i + 1) command_data.mask[i] = ~0; command_data.tag = TAG; + loop_valid = 0; input_byte_valid = 0; input_byte = 0; - zero_count = 0; + loop_count = 0; state = state.first; end else begin if (echo_ready) echo_valid = 0; @@ -54,8 +59,11 @@ module command_parser input_byte_valid = 1; input_byte = uart_data; end + if (loop_ready && loop_valid) begin + loop_valid = 0; + end - if (!command_valid) begin + if (!command_valid && !loop_valid) begin case (state) READ_COMMAND: if (input_byte_valid) begin @@ -63,18 +71,24 @@ module command_parser "@": begin command_data.address = 0; + loop_valid = 1; + loop_data = 0; state = READ_ADDRESS; end "?": begin command_valid = 1; command_data.write = 0; + loop_valid = 1; + loop_data = 0; end "=": begin command_data.write = 1; for (int i = 0; i < `RAM_LINE_WORDS; i = i + 1) command_data.data[i] = 0; + loop_valid = 1; + loop_data = 0; state = READ_DATA; end @@ -82,8 +96,14 @@ module command_parser command_data.write = 1; for (int i = 0; i < `RAM_LINE_WORDS; i = i + 1) command_data.data[i] = 0; - zero_count = 0; - state = READ_ZERO_COUNT; + loop_count = 0; + state = READ_LOOP_COUNT; + end + + "#": begin + command_data.write = 0; + loop_count = 0; + state = READ_LOOP_COUNT; end endcase @@ -129,27 +149,29 @@ module command_parser input_byte_valid = 0; end - READ_ZERO_COUNT: if (input_byte_valid) begin + READ_LOOP_COUNT: if (input_byte_valid) begin if (input_byte == ":") begin // ignore end else if (input_byte >= "0" && input_byte <= "9") begin - zero_count = zero_count << 4; - zero_count[3:0] = input_byte - "0"; + loop_count = loop_count << 4; + loop_count[3:0] = input_byte - "0"; end else if (input_byte >= "a" && input_byte <= "f") begin - zero_count = zero_count << 4; - zero_count[3:0] = input_byte - "a" + 10; + loop_count = loop_count << 4; + loop_count[3:0] = input_byte - "a" + 10; end else if (input_byte >= "A" && input_byte <= "F") begin - zero_count = zero_count << 4; - zero_count[3:0] = input_byte - "A" + 10; + loop_count = loop_count << 4; + loop_count[3:0] = input_byte - "A" + 10; end else begin - state = ZERO_MEMORY; + loop_valid = 1; + loop_data = 1; + state = LOOP_MEMORY; end input_byte_valid = 0; end -`ifdef SLOW_ZEROING - ZERO_MEMORY: if (!echo_valid) begin - if (zero_count == 0) begin +`ifdef SLOW_LOOPING + LOOP_MEMORY: if (!echo_valid) begin + if (loop_count == 0) begin echo_valid = 1; echo_data = "\n"; state = state.first; @@ -157,17 +179,18 @@ module command_parser echo_valid = 1; echo_data = "."; command_valid = 1; - --zero_count; + --loop_count; end end `else - ZERO_MEMORY: begin - if (zero_count == 0) begin + LOOP_MEMORY: begin + if (loop_count == 0) begin state = state.first; end else begin command_valid = 1; - if (--zero_count == 0) + if (--loop_count == 0) begin state = state.first; + end end end `endif diff --git a/hdl/result_printer.sv b/hdl/result_printer.sv index 6e1bd53..322fac0 100644 --- a/hdl/result_printer.sv +++ b/hdl/result_printer.sv @@ -11,15 +11,21 @@ module result_printer , input bit echo_ready , output bit echo_valid , output uart_byte_t echo_data + + , output bit loop_ready + , input bit loop_valid + , input bit loop_data ); bit hold_valid; ram_read_response_t hold; + bit loop; ram_byte_count_t byte_count; ram_word_count_t word_count; (* syn_encoding = "one-hot" *) enum int unsigned - { HIGH_NIBBLE + { EQUALS_SIGN + , HIGH_NIBBLE , LOW_NIBBLE , WORD_SEPARATOR } state; @@ -29,12 +35,16 @@ module result_printer result_ready = 0; echo_valid = 0; echo_data = 0; + loop_ready = 0; hold_valid = 0; + loop = 0; byte_count = 0; word_count = 0; state = state.first; end else begin if (echo_ready) echo_valid = 0; + if (loop_ready && loop_valid) + loop = loop_data; if (result_ready && result_valid) begin hold_valid = 1; hold = result_data; @@ -48,35 +58,44 @@ module result_printer automatic ram_word_t w = hold.data[word_count-1]; automatic ram_byte_t b = w[byte_count-1]; echo_valid = 1; + if (state == EQUALS_SIGN && !loop) + state = state.next; case (state) + EQUALS_SIGN: echo_data = "="; HIGH_NIBBLE: echo_data = b[7:4]; LOW_NIBBLE: echo_data = b[3:0]; WORD_SEPARATOR: echo_data = ":"; endcase - if (state != WORD_SEPARATOR) begin + if (state == HIGH_NIBBLE || state == LOW_NIBBLE) begin if (echo_data < 10) echo_data = echo_data + "0"; else echo_data = echo_data + "A" - 10; end - state = state.next; - if (state == WORD_SEPARATOR && (byte_count != 1 || word_count == 1)) - state = state.next; - if (state == state.first) begin - byte_count = byte_count - 1; - if (byte_count == 0) begin + if (state == LOW_NIBBLE) begin + if (byte_count == 1) begin byte_count = `RAM_WORD_BYTES; word_count = word_count - 1; + state = state.next; + end else begin + byte_count = byte_count - 1; + state = HIGH_NIBBLE; end + end else begin + state = state.next; end end else begin echo_valid = 1; - echo_data = "\n"; + if (loop && hold.address[3:0] != 'hf) + echo_data = " "; + else + echo_data = "\n"; hold_valid = 0; end end result_ready = !hold_valid; + loop_ready = 1; end end diff --git a/hdl/top.sv b/hdl/top.sv index 76c4d4d..03a2331 100644 --- a/hdl/top.sv +++ b/hdl/top.sv @@ -169,6 +169,10 @@ module top bit print_valid; ram_read_response_t print_data; + bit loop_ready; + bit loop_valid; + bit loop_data; + bit [`NUM_PDPS-1:0] pdp_command_ready; bit [`NUM_PDPS-1:0] pdp_command_valid; pdp_command_t [`NUM_PDPS-1:0] pdp_command_data; @@ -245,6 +249,10 @@ module top , .command_ready(command_ready) , .command_valid(command_valid) , .command_data(command_data) + + , .loop_ready(loop_ready) + , .loop_valid(loop_valid) + , .loop_data(loop_data) ); mem_arbiter memarb @@ -316,6 +324,10 @@ module top , .echo_ready(ram_echo_in1_ready) , .echo_valid(ram_echo_in1_valid) , .echo_data(ram_echo_in1_data) + + , .loop_ready(loop_ready) + , .loop_valid(loop_valid) + , .loop_data(loop_data) ); bit slow_clock; -- cgit v1.2.3