From 4541224c007a1818ffdcd69a7dc4a8e5392bb44d Mon Sep 17 00:00:00 2001 From: Julian Blake Kongslie Date: Sat, 26 Mar 2022 09:50:26 -0700 Subject: Add basic clock-domain-crossing FIFO. --- hdl/fifo.sv | 68 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 68 insertions(+) create mode 100644 hdl/fifo.sv diff --git a/hdl/fifo.sv b/hdl/fifo.sv new file mode 100644 index 0000000..4158067 --- /dev/null +++ b/hdl/fifo.sv @@ -0,0 +1,68 @@ +module fifo + #( type data_t = bit + + , DEPTH_BITS = 10 + ) + ( input bit clock_in + , input bit clock_out + , input bit reset + + , output bit in_ready + , input bit in_valid + , input data_t in_data + + , input bit out_ready + , output bit out_valid + , output data_t out_data + ); + + localparam DEPTH = 1<> 1); + + in_ready = oldest_grey != youngest_grey || youngest_wrap == oldest_wrap; + end + end + + always @(posedge clock_out, posedge reset) begin + if (reset) begin + out_valid = 0; + oldest = 0; + oldest_wrap = 0; + oldest_grey = 0; + end else begin + if (out_ready && out_valid) begin + if (++oldest == 0) + ++oldest_wrap; + end + + oldest_grey = oldest ^ (oldest >> 1); + + out_valid = oldest_grey != youngest_grey || youngest_wrap != oldest_wrap; + out_data = data[oldest]; + end + end + +endmodule -- cgit v1.2.3