From 55d1bc2bc007f48a429ddf556df58d59fdc0f657 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 27 Mar 2022 16:58:16 -0700
Subject: Reduce internal clock speed to 30MHz.

---
 altera/clocks.sdc | 2 +-
 hdl/top.sv        | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/altera/clocks.sdc b/altera/clocks.sdc
index c08f897..fd99dad 100644
--- a/altera/clocks.sdc
+++ b/altera/clocks.sdc
@@ -1,3 +1,3 @@
 # This is the clock for timing analysis, not timing-driven synthesis.
 # See init.tcl for the other clock.
-create_clock -period "50 MHz" clock
+create_clock -period "30 MHz" clock
diff --git a/hdl/top.sv b/hdl/top.sv
index f4a64f9..38ab638 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -19,8 +19,8 @@ module top
     bit internal_clock;
     bit internal_reset;
     pll
-        #(  .MULTIPLY_BY(1)
-        ,   .DIVIDE_BY(1)
+        #(  .MULTIPLY_BY(3)
+        ,   .DIVIDE_BY(5)
         ) fastpll
         (   .native_clk(clock)
         ,   .reset_n(resetn)
-- 
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