From 38c5ae5b60eae9562b97da42f47af3861847f8e5 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 8 May 2022 15:51:35 -0700
Subject: *Proper* serial port for memory downloads. 115200 8O2 RS232 with
 CRTRTS.

---
 altera/clocks.sdc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'altera/clocks.sdc')

diff --git a/altera/clocks.sdc b/altera/clocks.sdc
index fd99dad..c08f897 100644
--- a/altera/clocks.sdc
+++ b/altera/clocks.sdc
@@ -1,3 +1,3 @@
 # This is the clock for timing analysis, not timing-driven synthesis.
 # See init.tcl for the other clock.
-create_clock -period "30 MHz" clock
+create_clock -period "50 MHz" clock
-- 
cgit v1.2.3