From 0553c4839c06011bd044f69b4913e5c793fdd2ec Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 27 Feb 2022 17:21:05 -0800
Subject: Initial commit.

---
 altera/clocks.sdc |  3 +++
 altera/jtag.cdf   | 12 ++++++++++++
 2 files changed, 15 insertions(+)
 create mode 100644 altera/clocks.sdc
 create mode 100644 altera/jtag.cdf

(limited to 'altera')

diff --git a/altera/clocks.sdc b/altera/clocks.sdc
new file mode 100644
index 0000000..c08f897
--- /dev/null
+++ b/altera/clocks.sdc
@@ -0,0 +1,3 @@
+# This is the clock for timing analysis, not timing-driven synthesis.
+# See init.tcl for the other clock.
+create_clock -period "50 MHz" clock
diff --git a/altera/jtag.cdf b/altera/jtag.cdf
new file mode 100644
index 0000000..ac80090
--- /dev/null
+++ b/altera/jtag.cdf
@@ -0,0 +1,12 @@
+JedecChain;
+    FileRevision(JESD32A);
+    DefaultMfr(6E);
+
+    P ActionCode(Ign)
+        Device PartName(10CL025Y) MfrSpec(OpMask(0));
+
+ChainEnd;
+
+AlteraBegin;
+    ChainType(JTAG);
+AlteraEnd;
-- 
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