From 55d1bc2bc007f48a429ddf556df58d59fdc0f657 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 27 Mar 2022 16:58:16 -0700
Subject: Reduce internal clock speed to 30MHz.

---
 altera/clocks.sdc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'altera')

diff --git a/altera/clocks.sdc b/altera/clocks.sdc
index c08f897..fd99dad 100644
--- a/altera/clocks.sdc
+++ b/altera/clocks.sdc
@@ -1,3 +1,3 @@
 # This is the clock for timing analysis, not timing-driven synthesis.
 # See init.tcl for the other clock.
-create_clock -period "50 MHz" clock
+create_clock -period "30 MHz" clock
-- 
cgit v1.2.3