From 6492ed239dcd5724acb90723e16c2d5110f2b0b8 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 20 Mar 2022 13:11:05 -0700
Subject: Temporary change to PDP-8 internal memory to match controller
 protocol

---
 hdl/core.sv | 143 ++++++++++++++++++++++++++++++++++++------------------------
 1 file changed, 86 insertions(+), 57 deletions(-)

(limited to 'hdl/core.sv')

diff --git a/hdl/core.sv b/hdl/core.sv
index a71e318..8bbea98 100644
--- a/hdl/core.sv
+++ b/hdl/core.sv
@@ -1,60 +1,84 @@
+`include "defs.svh"
+
 `ifdef SYNTHESIS
 `define lag(x) x
 `else
 `define lag(x) $past(x)
 `endif
 
+`define DATA_BITS 12
+
 module mem
     (   input   bit clk
     ,   input   bit reset
 
-    ,   output  bit                 ready
-    ,   input   bit                 valid
-    ,   input   bit                 write
-    ,   input   bit [ADDR_BITS-1:0] address
-    ,   input   bit [DATA_BITS-1:0] write_data
+    ,   output  bit                 command_ready
+    ,   input   bit                 command_valid
+    ,   input   pdp_command_t       command_data
 
+    ,   input   bit                 read_ready
     ,   output  bit                 read_valid
-    ,   output  bit [DATA_BITS-1:0] read_data
+    ,   output  pdp_read_response_t read_data
     );
 
-parameter ADDR_BITS;
-parameter DATA_BITS;
 parameter INIT_FILE;
 
-bit [DATA_BITS-1:0] storage [0:(1<<ADDR_BITS)-1];
+bit             hold_valid;
+pdp_command_t   hold;
+
+bit [`DATA_BITS-1:0] storage [0:(1 << `PDP_ADDRESS_BITS)-1];
 initial $readmemh(INIT_FILE, storage);
 
 always_ff @(posedge clk) begin
     if (reset) begin
-        ready = 0;
+        command_ready = 0;
         read_valid = 0;
+        hold_valid = 0;
     end else begin
-        read_valid = 0;
-        if (ready && `lag(valid)) begin
-            if (`lag(write)) begin
-                storage[`lag(address)] = `lag(write_data);
-            end else begin
-                read_valid = 1;
-                read_data = storage[`lag(address)];
+        if (read_ready) read_valid = 0;
+
+        if (command_ready && command_valid) begin
+            hold_valid = 1;
+            hold = command_data;
+        end
+
+        if (hold_valid && hold.write) begin
+//            for (int i = 0; i < `RAM_LINE_WORDS; ++i) begin
+                if (hold.mask[0]) begin
+                    automatic pdp_word_address_t addr = 0;
+                    addr[`PDP_ADDRESS_BITS-1:$clog2(`RAM_LINE_WORDS)] = hold.address;
+//                    if (`RAM_LINE_WORDS != 1)
+//                        addr[$clog2(`RAM_LINE_WORDS)-1:0] = i;
+                    storage[addr] = hold.data[/*i*/0];
+                end
+//            end
+            hold_valid = 0;
+        end else if (hold_valid && !read_valid) begin
+            read_valid = 1;
+            read_data.address = hold.address;
+            /*for (int i = 0; i < `RAM_LINE_WORDS; ++i)*/ begin
+                automatic pdp_word_address_t addr = 0;
+                addr[`PDP_ADDRESS_BITS-1:$clog2(`RAM_LINE_WORDS)] = hold.address;
+//                if (`RAM_LINE_WORDS != 1)
+//                    addr[$clog2(`RAM_LINE_WORDS)-1:0] = i;
+                read_data.data[/*i*/0] = storage[addr];
             end
+            hold_valid = 0;
         end
-        ready = 1;
+
+        command_ready = !hold_valid;
     end
 end
 
 endmodule
 
 module core
-    #(  ADDR_BITS   = 15
-    ,   DATA_BITS   = 12
-    )
     (   input   bit clk
     ,   input   bit reset
 
     ,   input   bit [2:0] switch_df
     ,   input   bit [2:0] switch_if
-    ,   input   bit [ADDR_BITS-3-1:0] switch_sr
+    ,   input   bit [`PDP_ADDRESS_BITS-3-1:0] switch_sr
     ,   input   bit switch_start
     ,   input   bit switch_load_add
     ,   input   bit switch_dep
@@ -65,11 +89,11 @@ module core
     ,   input   bit switch_sing_inst
 
     // verilator lint_off UNDRIVEN
-    ,   output  bit [ADDR_BITS-3-1:0] led_pc
-    ,   output  bit [ADDR_BITS-3-1:0] led_memaddr
-    ,   output  bit [DATA_BITS-1:0] led_memdata
-    ,   output  bit [DATA_BITS-1:0] led_acc
-    ,   output  bit [DATA_BITS-1:0] led_mq
+    ,   output  bit [`PDP_ADDRESS_BITS-3-1:0] led_pc
+    ,   output  bit [`PDP_ADDRESS_BITS-3-1:0] led_memaddr
+    ,   output  bit [`DATA_BITS-1:0] led_memdata
+    ,   output  bit [`DATA_BITS-1:0] led_acc
+    ,   output  bit [`DATA_BITS-1:0] led_mq
     ,   output  bit led_and
     ,   output  bit led_tad
     ,   output  bit led_isz
@@ -137,32 +161,37 @@ assign led_ion = int_enable;
 bit mem_ready;
 bit mem_valid;
 bit mem_write;
-bit [ADDR_BITS-1:0] mem_address;
-bit [DATA_BITS-1:0] mem_write_data;
+bit [`PDP_ADDRESS_BITS-1:0] mem_address;
+bit [`DATA_BITS-1:0] mem_write_data;
 assign led_current_address = mem_valid;
 
-assign led_memaddr = mem_address[ADDR_BITS-3-1:0];
+assign led_memaddr = mem_address[`PDP_ADDRESS_BITS-3-1:0];
 
 bit mem_read_valid;
-bit [DATA_BITS-1:0] mem_read_data;
+bit [`DATA_BITS-1:0] mem_read_data;
+
+pdp_command_t mem_command;
+pdp_read_response_t mem_response;
+
+assign mem_command.address = mem_address;
+assign mem_command.write = mem_write;
+assign mem_command.data = mem_write_data;
+assign mem_command.mask = ~0;
+assign mem_read_data = mem_response.data;
 
 mem
-    #(  .ADDR_BITS(ADDR_BITS)
-    ,   .DATA_BITS(DATA_BITS)
-    ,   .INIT_FILE("mem/focal69.loaded.hex")
-    )
-    memory
+    #(   .INIT_FILE("mem/focal69.loaded.hex")
+    ) memory
     (   .clk(clk)
     ,   .reset(reset)
 
-    ,   .ready(mem_ready)
-    ,   .valid(mem_valid)
-    ,   .address(mem_address)
-    ,   .write(mem_write)
-    ,   .write_data(mem_write_data)
+    ,   .command_ready(mem_ready)
+    ,   .command_valid(mem_valid)
+    ,   .command_data(mem_command)
 
+    ,   .read_ready(1)
     ,   .read_valid(mem_read_valid)
-    ,   .read_data(mem_read_data)
+    ,   .read_data(mem_response)
     );
 
 bit rx_ready;
@@ -191,19 +220,19 @@ alt_jtag_atlantic
     ,   .t_ena(rx_valid)
     );
 
-bit [ADDR_BITS-3-1:7] page;
+bit [`PDP_ADDRESS_BITS-3-1:7] page;
 
 bit [2:0] data_field;
 bit [2:0] data_field_saved;
 bit [2:0] inst_field;
 bit [2:0] inst_field_buffer;
 bit [2:0] inst_field_saved;
-bit [ADDR_BITS-3-1:0] pc;
-bit [ADDR_BITS-3-1:0] next_pc;
+bit [`PDP_ADDRESS_BITS-3-1:0] pc;
+bit [`PDP_ADDRESS_BITS-3-1:0] next_pc;
 assign led_pc = pc;
 bit [2:0] opcode;
 bit [8:0] operand;
-bit [DATA_BITS-1:0] acc;
+bit [`DATA_BITS-1:0] acc;
 bit link;
 
 assign led_df = data_field;
@@ -223,7 +252,7 @@ assign led_opr = opcode == 7;
 
 bit tti_int_enable;
 bit tti_valid;
-bit [DATA_BITS-1:0] tti_data;
+bit [`DATA_BITS-1:0] tti_data;
 
 bit [15:0] tto_delay;
 bit tto_int_enable;
@@ -233,7 +262,7 @@ bit tto_flag_old;
 bit i;
 bit z;
 bit [6:0] wip;
-bit [ADDR_BITS-1:0] address;
+bit [`PDP_ADDRESS_BITS-1:0] address;
 
 bit can_skip;
 bit skip;
@@ -398,7 +427,7 @@ always_ff @(posedge clk) begin
                     mem_write = 0;
                     if (`lag(mem_ready)) begin
                         state = DECODE;
-                        page = pc[ADDR_BITS-3-1:7];
+                        page = pc[`PDP_ADDRESS_BITS-3-1:7];
                         next_pc = pc + 1;
                     end
                 end
@@ -454,7 +483,7 @@ always_ff @(posedge clk) begin
                                 if (i) begin
                                     state = INDIRECT;
                                 end else begin
-                                    next_pc = address[ADDR_BITS-3-1:0];
+                                    next_pc = address[`PDP_ADDRESS_BITS-3-1:0];
                                     inst_field = inst_field_buffer;
                                 end
                             end
@@ -681,7 +710,7 @@ always_ff @(posedge clk) begin
                             led_memdata = `lag(mem_read_data);
                             address = {3'b0, `lag(mem_read_data)};
                             address += 1;
-                            address[ADDR_BITS-1:ADDR_BITS-3] = data_field;
+                            address[`PDP_ADDRESS_BITS-1:`PDP_ADDRESS_BITS-3] = data_field;
                             state = PREINC;
                         end else begin
                             led_memdata = `lag(mem_read_data);
@@ -690,7 +719,7 @@ always_ff @(posedge clk) begin
                                 'o0, 'o1, 'o2: state = AGEN;
                                 'o3, 'o4: state = EXEC;
                                 'o5: begin
-                                    next_pc = address[ADDR_BITS-3-1:0];
+                                    next_pc = address[`PDP_ADDRESS_BITS-3-1:0];
                                     $display("indirect jump to %o", next_pc);
                                     inst_field = inst_field_buffer;
                                     state = RETIRE;
@@ -703,7 +732,7 @@ always_ff @(posedge clk) begin
                 PREINC: begin
                     mem_valid = 1;
                     mem_write = 1;
-                    mem_write_data = address[DATA_BITS-1:0];
+                    mem_write_data = address[`DATA_BITS-1:0];
                     led_memdata = mem_write_data;
                     $display("preinc [%o] <- %o", mem_address, mem_write_data);
                     case (opcode)
@@ -762,15 +791,15 @@ always_ff @(posedge clk) begin
                                 mem_valid = 1;
                                 mem_address = address;
                                 mem_write = 1;
-                                mem_write_data = next_pc[DATA_BITS-1:0];
+                                mem_write_data = next_pc[`DATA_BITS-1:0];
                                 led_memdata = mem_write_data;
                                 $display("store [%o] <- %o", mem_address, mem_write_data);
-                                next_pc = address[ADDR_BITS-3-1:0] + 1;
+                                next_pc = address[`PDP_ADDRESS_BITS-3-1:0] + 1;
                                 inst_field = inst_field_buffer;
                                 state = MEMWAIT;
                             end
                             'o5: begin
-                                next_pc = address[ADDR_BITS-3-1:0];
+                                next_pc = address[`PDP_ADDRESS_BITS-3-1:0];
                                 inst_field = inst_field_buffer;
                             end
                         endcase
@@ -788,7 +817,7 @@ always_ff @(posedge clk) begin
                 DEPOSIT: begin
                     if (`lag(mem_ready)) begin
                         state = FETCH; // Not a retired instruction; go directly to decode
-                        page = pc[ADDR_BITS-3-1:7];
+                        page = pc[`PDP_ADDRESS_BITS-3-1:7];
                         ++pc; // Not a skip; normal part of panel deposit (because we are skipping RETIRE)
                         run = 0;
                     end
-- 
cgit v1.2.3