From 1aeb760d093189486efbf5adf3292881eda94eb0 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 24 Jul 2022 14:59:03 -0700
Subject: Writeback cache using explicit altsyncram instead of inferred memory.

---
 hdl/defs.svh | 3 ++-
 1 file changed, 2 insertions(+), 1 deletion(-)

(limited to 'hdl/defs.svh')

diff --git a/hdl/defs.svh b/hdl/defs.svh
index 73fddaf..dc4a243 100644
--- a/hdl/defs.svh
+++ b/hdl/defs.svh
@@ -5,7 +5,7 @@
 
 `define PDP_ADDRESS_BITS    15
 
-`define NUM_PDPS            4
+`define NUM_PDPS            8
 
 `define UART_BYTE_BITS      8
 
@@ -56,5 +56,6 @@ typedef struct packed {
 typedef struct packed {
     pdp_line_address_t  address;
     bit                 snoop;
+    bit                 data_valid;
     ram_line_t          data;
 } mem_to_core_t;
-- 
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