From 1aeb760d093189486efbf5adf3292881eda94eb0 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 24 Jul 2022 14:59:03 -0700
Subject: Writeback cache using explicit altsyncram instead of inferred memory.

---
 hdl/mem_broadcast.sv | 2 ++
 1 file changed, 2 insertions(+)

(limited to 'hdl/mem_broadcast.sv')

diff --git a/hdl/mem_broadcast.sv b/hdl/mem_broadcast.sv
index 599be28..e86873e 100644
--- a/hdl/mem_broadcast.sv
+++ b/hdl/mem_broadcast.sv
@@ -48,6 +48,8 @@ module mem_broadcast
                     if (!pdp_valid[ram_data.tag-1]) begin
                         pdp_valid[ram_data.tag-1] = 1;
                         pdp_data[ram_data.tag-1].address = hold_data.address[`PDP_ADDRESS_BITS-1:$clog2(`RAM_LINE_WORDS)];
+                        pdp_data[ram_data.tag-1].snoop = 0;
+                        pdp_data[ram_data.tag-1].data_valid = 1;
                         pdp_data[ram_data.tag-1].data = hold_data.data;
                         hold_valid = 0;
                     end
-- 
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