From fce46a9a7bb2fe2a9b3addca0f488931b9e231ff Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 13 Mar 2022 16:50:34 -0700
Subject: Add memory arbiter and broadcast in between command UART and DRAM.

---
 hdl/mem_broadcast.sv | 61 ++++++++++++++++++++++++++++++++++++++++++++++++++++
 1 file changed, 61 insertions(+)
 create mode 100644 hdl/mem_broadcast.sv

(limited to 'hdl/mem_broadcast.sv')

diff --git a/hdl/mem_broadcast.sv b/hdl/mem_broadcast.sv
new file mode 100644
index 0000000..720699b
--- /dev/null
+++ b/hdl/mem_broadcast.sv
@@ -0,0 +1,61 @@
+`include "defs.svh"
+
+module mem_broadcast
+    (   input   bit                                 clock
+    ,   input   bit                                 reset
+
+    ,   output  bit                                 ram_ready
+    ,   input   bit                                 ram_valid
+    ,   input   ram_read_response_t                 ram_data
+
+    ,   input   bit                                 print_ready
+    ,   output  bit                                 print_valid
+    ,   output  ram_read_response_t                 print_data
+
+    ,   input   bit                 [`NUM_PDPS-1:0] pdp_ready
+    ,   output  bit                 [`NUM_PDPS-1:0] pdp_valid
+    ,   output  pdp_read_response_t [`NUM_PDPS-1:0] pdp_data
+    );
+
+    bit                 hold_valid;
+    ram_read_response_t hold_data;
+
+    always @(posedge clock) begin
+        if (reset) begin
+            ram_ready = 0;
+            print_valid = 0;
+            for (int i = 0; i < `NUM_PDPS; ++i)
+                pdp_valid[i] = 0;
+            hold_valid = 0;
+        end else begin
+            if (print_ready) print_valid = 0;
+            for (int i = 0; i < `NUM_PDPS; ++i)
+                if (pdp_ready[i]) pdp_valid[i] = 0;
+
+            if (ram_ready && ram_valid) begin
+                hold_valid = 1;
+                hold_data = ram_data;
+            end
+
+            if (hold_valid) begin
+                if (hold_data.tag == 0) begin
+                    if (!print_valid) begin
+                        print_valid = 1;
+                        print_data = hold_data;
+                        hold_valid = 0;
+                    end
+                end else begin
+                    if (!pdp_valid[ram_data.tag-1]) begin
+                        pdp_valid[ram_data.tag-1] = 1;
+                        pdp_data[ram_data.tag-1].address = hold_data.address[`PDP_ADDRESS_BITS-1:$clog2(`RAM_LINE_WORDS)];
+                        pdp_data[ram_data.tag-1].data = hold_data.data;
+                        hold_valid = 0;
+                    end
+                end
+            end
+
+            ram_ready = !hold_valid;
+        end
+    end
+
+endmodule
-- 
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