From 1a47b552cca074b47c048c3428c92dfb2e3f23b1 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 8 May 2022 17:20:57 -0700
Subject: Demand that CTS is asserted for multiple symbol periods before
 transmit.

---
 hdl/rs232.sv | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

(limited to 'hdl/rs232.sv')

diff --git a/hdl/rs232.sv b/hdl/rs232.sv
index ef53f12..2949201 100644
--- a/hdl/rs232.sv
+++ b/hdl/rs232.sv
@@ -3,6 +3,7 @@
 module rs232_tx
     #(  PARITY      = 0
     ,   STOP_BITS   = 2
+    ,   CTS_BITS    = 3
     )
     (   input   bit         clock
     ,   input   bit         reset
@@ -29,6 +30,8 @@ module rs232_tx
     bit [$clog2($bits(uart_byte_t)):0]  data_bits;
     bit [$clog2(STOP_BITS):0]           stop_bits;
 
+    bit [CTS_BITS-1:0]    cts_samples;
+
     always @(posedge clock, posedge reset) begin
         if (reset) begin
             out_ready = 0;
@@ -38,6 +41,7 @@ module rs232_tx
             state = state.first;
             data_bits = 0;
             stop_bits = 0;
+            cts_samples = 0;
         end else begin
             if (out_ready && out_valid) begin
                 hold_valid = 1;
@@ -48,11 +52,14 @@ module rs232_tx
                 stop_bits = 0;
             end
 
+            cts_samples = cts_samples << 1;
+            cts_samples[0] = cts;
+
             if (hold_valid) begin
                 case (state)
 
                     START: begin
-                        if (!cts) begin
+                        if (cts_samples == 0) begin
                             tx = 0;
                             state = state.next;
                         end
-- 
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