From 1aa35d02a3675a2da94f264364681ee7b71111fb Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Fri, 22 Apr 2022 22:43:36 -0700
Subject: Transmit and receive an even parity bit in RS232 uart.

---
 hdl/rs232.sv | 23 +++++++++++++++++++++++
 1 file changed, 23 insertions(+)

(limited to 'hdl/rs232.sv')

diff --git a/hdl/rs232.sv b/hdl/rs232.sv
index 41403a6..420f273 100644
--- a/hdl/rs232.sv
+++ b/hdl/rs232.sv
@@ -13,10 +13,12 @@ module rs232_tx
 
     bit         hold_valid;
     uart_byte_t hold;
+    bit         parity;
 
     (* syn_encoding = "one-hot" *) enum int unsigned
         {   START
         ,   DATA
+        ,   PARITY
         ,   STOP1
         ,   STOP2
         } state;
@@ -28,12 +30,14 @@ module rs232_tx
             out_ready = 0;
             tx = 1;
             hold_valid = 0;
+            parity = 0;
             state = state.first;
             data_bits = 0;
         end else begin
             if (out_ready && out_valid) begin
                 hold_valid = 1;
                 hold = out_data;
+                parity = 0;
                 state = state.first;
                 data_bits = 0;
             end
@@ -48,12 +52,18 @@ module rs232_tx
 
                     DATA: begin
                         tx = hold[data_bits];
+                        parity = parity ^ tx;
                         if (data_bits == `UART_BYTE_BITS-1)
                             state = state.next;
                         else
                             ++data_bits;
                     end
 
+                    PARITY: begin
+                        tx = parity;
+                        state = state.next;
+                    end
+
                     STOP1: begin
                         tx = 1;
                         state = state.next;
@@ -90,11 +100,13 @@ module rs232_rx
     (* syn_encoding = "one-hot" *) enum int unsigned
         {   START
         ,   DATA
+        ,   PARITY
         ,   STOP
         } state;
 
     uart_byte_t                             buffer;
     bit         [$clog2(`UART_BYTE_BITS):0] data_bits;
+    bit                                     parity;
 
     always @(posedge clock) begin
         if (reset) begin
@@ -102,6 +114,7 @@ module rs232_rx
             state = state.first;
             buffer = 0;
             data_bits = 0;
+            parity = 0;
         end else begin
             if (in_ready && in_valid)
                 in_valid = 0;
@@ -113,17 +126,27 @@ module rs232_rx
                         state = state.next;
                         buffer = 0;
                         data_bits = 0;
+                        parity = 0;
                     end
                 end
 
                 DATA: begin
                     buffer[data_bits] = rx;
+                    parity = parity ^ rx;
                     if (data_bits == `UART_BYTE_BITS-1)
                         state = state.next;
                     else
                         ++data_bits;
                 end
 
+                PARITY: begin
+                    parity = parity ^ rx;
+                    if (parity == 0)
+                        state = state.next;
+                    else
+                        state = state.first;
+                end
+
                 STOP: begin
                     if (!in_valid && rx == 1) begin
                         in_valid = 1;
-- 
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