From 1bc6bb6857357e3cd2b3756bd9608db86e1fa456 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 17 Apr 2022 15:57:29 -0700
Subject: Working (but very slow) RS232 UART

---
 hdl/rs232.sv | 26 ++++++++++++++------------
 1 file changed, 14 insertions(+), 12 deletions(-)

(limited to 'hdl/rs232.sv')

diff --git a/hdl/rs232.sv b/hdl/rs232.sv
index 2f631f8..03378ef 100644
--- a/hdl/rs232.sv
+++ b/hdl/rs232.sv
@@ -20,7 +20,7 @@ module rs232_tx
         ,   STOP
         } state;
 
-    bit [$clog2(`UART_BYTE_BITS+1):0]   data_bits;
+    bit [$clog2(`UART_BYTE_BITS):0] data_bits;
 
     always @(posedge clock) begin
         if (reset) begin
@@ -34,7 +34,7 @@ module rs232_tx
                 hold_valid = 1;
                 hold = out_data;
                 state = state.first;
-                data_bits = `UART_BYTE_BITS;
+                data_bits = 0;
             end
 
             if (hold_valid) begin
@@ -46,10 +46,11 @@ module rs232_tx
                     end
 
                     DATA: begin
-                        --data_bits;
-                        tx = !out_data[data_bits];
-                        if (data_bits == 0)
+                        tx = hold[data_bits];
+                        if (data_bits == `UART_BYTE_BITS-1)
                             state = state.next;
+                        else
+                            ++data_bits;
                     end
 
                     STOP: begin
@@ -86,8 +87,8 @@ module rs232_rx
         ,   STOP
         } state;
 
-    uart_byte_t                                 buffer;
-    bit         [$clog2(`UART_BYTE_BITS+1):0]   data_bits;
+    uart_byte_t                             buffer;
+    bit         [$clog2(`UART_BYTE_BITS):0] data_bits;
 
     always @(posedge clock) begin
         if (reset) begin
@@ -105,21 +106,22 @@ module rs232_rx
                     if (rx == 0) begin
                         state = state.next;
                         buffer = 0;
-                        data_bits = `UART_BYTE_BITS;
+                        data_bits = 0;
                     end
                 end
 
                 DATA: begin
-                    --data_bits;
-                    buffer[data_bits] = !rx;
-                    if (data_bits == 0)
+                    buffer[data_bits] = rx;
+                    if (data_bits == `UART_BYTE_BITS-1)
                         state = state.next;
+                    else
+                        ++data_bits;
                 end
 
                 STOP: begin
                     if (!in_valid && rx == 1) begin
                         in_valid = 1;
-                        in_data = data_bits;
+                        in_data = buffer;
                     end
                     state = state.next;
                 end
-- 
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