From c9697a5bc6e315be8441223fbb07d00e57547e2f Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 15 May 2022 15:50:21 -0700
Subject: Consistent RS232 wire names (DCE side names is used everywhere)

---
 hdl/rs232.sv | 54 +++++++++++++++++++++++++++---------------------------
 1 file changed, 27 insertions(+), 27 deletions(-)

(limited to 'hdl/rs232.sv')

diff --git a/hdl/rs232.sv b/hdl/rs232.sv
index 2949201..b898a9c 100644
--- a/hdl/rs232.sv
+++ b/hdl/rs232.sv
@@ -3,7 +3,7 @@
 module rs232_tx
     #(  PARITY      = 0
     ,   STOP_BITS   = 2
-    ,   CTS_BITS    = 3
+    ,   RTS_BITS    = 3
     )
     (   input   bit         clock
     ,   input   bit         reset
@@ -12,8 +12,8 @@ module rs232_tx
     ,   input   bit         out_valid
     ,   input   uart_byte_t out_data
 
-    ,   output  bit         tx
-    ,   input   bit         cts
+    ,   output  bit         rxd
+    ,   input   bit         rts
     );
 
     bit         hold_valid;
@@ -30,18 +30,18 @@ module rs232_tx
     bit [$clog2($bits(uart_byte_t)):0]  data_bits;
     bit [$clog2(STOP_BITS):0]           stop_bits;
 
-    bit [CTS_BITS-1:0]    cts_samples;
+    bit [RTS_BITS-1:0]    rts_samples;
 
     always @(posedge clock, posedge reset) begin
         if (reset) begin
             out_ready = 0;
-            tx = 1;
+            rxd = 1;
             hold_valid = 0;
             parity = PARITY;
             state = state.first;
             data_bits = 0;
             stop_bits = 0;
-            cts_samples = 0;
+            rts_samples = 0;
         end else begin
             if (out_ready && out_valid) begin
                 hold_valid = 1;
@@ -52,23 +52,23 @@ module rs232_tx
                 stop_bits = 0;
             end
 
-            cts_samples = cts_samples << 1;
-            cts_samples[0] = cts;
+            rts_samples = rts_samples << 1;
+            rts_samples[0] = rts;
 
             if (hold_valid) begin
                 case (state)
 
                     START: begin
-                        if (cts_samples == 0) begin
-                            tx = 0;
+                        if (rts_samples == 0) begin
+                            rxd = 0;
                             state = state.next;
                         end
                     end
 
                     DATA: begin
-                        tx = hold[0];
+                        rxd = hold[0];
                         hold = hold >> 1;
-                        parity = parity ^ tx;
+                        parity = parity ^ rxd;
                         if (data_bits == `UART_BYTE_BITS-1)
                             state = state.next;
                         else
@@ -76,12 +76,12 @@ module rs232_tx
                     end
 
                     PARITY_BIT: begin
-                        tx = parity;
+                        rxd = parity;
                         state = state.next;
                     end
 
                     STOP: begin
-                        tx = 1;
+                        rxd = 1;
                         if (stop_bits == STOP_BITS-1) begin
                             hold_valid = 0;
                             state = state.next;
@@ -92,7 +92,7 @@ module rs232_tx
 
                 endcase
             end else begin
-                tx = 1;
+                rxd = 1;
             end
 
             out_ready = !hold_valid;
@@ -114,8 +114,8 @@ module rs232_rx
     ,   output  bit         in_valid
     ,   output  uart_byte_t in_data
 
-    ,   input   bit         rx
-    ,   output  bit         rts
+    ,   input   bit         txd
+    ,   output  bit         cts
     );
 
     (* syn_encoding = "one-hot" *) enum int unsigned
@@ -138,7 +138,7 @@ module rs232_rx
         if (reset) begin
             clock_out = 0;
             in_valid = 0;
-            rts = 1;
+            cts = 1;
             state = state.first;
             buffer = 0;
             data_bits = 0;
@@ -174,7 +174,7 @@ module rs232_rx
                 case (state)
 
                     START: begin
-                        if (rx == 0) begin
+                        if (txd == 0) begin
                             state = state.next;
                             if (OVERSAMPLE == 0)
                                 state = state.next;
@@ -189,8 +189,8 @@ module rs232_rx
 
                     DATA: begin
                         buffer = buffer >> 1;
-                        buffer[`UART_BYTE_BITS-1] = rx;
-                        parity = parity ^ rx;
+                        buffer[`UART_BYTE_BITS-1] = txd;
+                        parity = parity ^ txd;
                         if (data_bits == `UART_BYTE_BITS-1)
                             state = state.next;
                         else
@@ -198,33 +198,33 @@ module rs232_rx
                     end
 
                     PARITY_BIT: begin
-                        parity = parity ^ rx;
+                        parity = parity ^ txd;
                         state = state.next;
                     end
 
                     STOP: begin
-                        if (!in_valid && rx == 1 && parity == 0) begin
+                        if (!in_valid && txd == 1 && parity == 0) begin
                             in_valid = 1;
                             in_data = buffer;
                         end
-                        if (rx == 1 && parity == 0) begin
+                        if (txd == 1 && parity == 0) begin
                             clock_counter = (OVERSAMPLE+1)/2;
                         end
-                        if (rx == 1)
+                        if (txd == 1)
                             state = state.first;
                         else
                             state = state.next;
                     end
 
                     REALSTOP: begin
-                        if (rx == 1)
+                        if (txd == 1)
                             state = state.first;
                     end
 
                 endcase
             end
 
-            rts = !(state == state.first && !in_valid);
+            cts = !(state == state.first && !in_valid);
         end
     end
 
-- 
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