From 1aeb760d093189486efbf5adf3292881eda94eb0 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 24 Jul 2022 14:59:03 -0700
Subject: Writeback cache using explicit altsyncram instead of inferred memory.

---
 hdl/top.sv | 6 ++----
 1 file changed, 2 insertions(+), 4 deletions(-)

(limited to 'hdl/top.sv')

diff --git a/hdl/top.sv b/hdl/top.sv
index 96b7510..7d6ba8e 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -493,9 +493,7 @@ module top
 `else
             mem_cache cache
                 (   .clock(internal_clock)
-                ,   .reset(internal_reset)
-
-                ,   .clear(clear_caches)
+                ,   .reset(internal_reset || clear_caches)
 
                 ,   .core_command_ready(cache_command_ready)
                 ,   .core_command_valid(cache_command_valid)
@@ -517,7 +515,7 @@ module top
 
             core cpu
                 (   .clk(internal_clock)
-                ,   .reset(internal_reset)
+                ,   .reset(internal_reset || clear_caches)
 
                 ,   .uart_tx_ready(tx_ready)
                 ,   .uart_tx_valid(tx_valid)
-- 
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