From 9ce65b7d3573d92e1d98a13b58a5d5763ba073c5 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 5 Jun 2022 15:34:23 -0700
Subject: Working L1 cache.

---
 hdl/top.sv | 51 +++++++++++++++++++++++++++++++++++++++++++++------
 1 file changed, 45 insertions(+), 6 deletions(-)

(limited to 'hdl/top.sv')

diff --git a/hdl/top.sv b/hdl/top.sv
index 03a2331..26006be 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -470,6 +470,45 @@ module top
             bit         rx_valid;
             uart_byte_t rx_data;
 
+            bit             cache_command_ready;
+            bit             cache_command_valid;
+            pdp_command_t   cache_command_data;
+
+            bit                 cache_response_ready;
+            bit                 cache_response_valid;
+            pdp_read_response_t cache_response_data;
+
+`ifdef NO_L1_CACHE
+            assign cache_command_ready = pdp_command_ready[i];
+            assign pdp_command_valid[i] = cache_command_valid;
+            assign pdp_command_data[i] = cache_command_data;
+
+            assign pdp_response_ready[i] = cache_response_ready;
+            assign cache_response_valid = pdp_response_valid[i];
+            assign cache_response_data = pdp_response_data[i];
+`else
+            mem_cache cache
+                (   .clock(internal_clock)
+                ,   .reset(internal_reset)
+
+                ,   .core_command_ready(cache_command_ready)
+                ,   .core_command_valid(cache_command_valid)
+                ,   .core_command_data(cache_command_data)
+
+                ,   .ram_command_ready(pdp_command_ready[i])
+                ,   .ram_command_valid(pdp_command_valid[i])
+                ,   .ram_command_data(pdp_command_data[i])
+
+                ,   .ram_response_ready(pdp_response_ready[i])
+                ,   .ram_response_valid(pdp_response_valid[i])
+                ,   .ram_response_data(pdp_response_data[i])
+
+                ,   .core_response_ready(cache_response_ready)
+                ,   .core_response_valid(cache_response_valid)
+                ,   .core_response_data(cache_response_data)
+                );
+`endif
+
             core cpu
                 (   .clk(internal_clock)
                 ,   .reset(internal_reset)
@@ -482,13 +521,13 @@ module top
                 ,   .uart_rx_valid(rx_valid)
                 ,   .uart_rx_data(rx_data)
 
-                ,   .mem_command_ready(pdp_command_ready[i])
-                ,   .mem_command_valid(pdp_command_valid[i])
-                ,   .mem_command(pdp_command_data[i])
+                ,   .mem_command_ready(cache_command_ready)
+                ,   .mem_command_valid(cache_command_valid)
+                ,   .mem_command(cache_command_data)
 
-                ,   .mem_read_ready(pdp_response_ready[i])
-                ,   .mem_read_valid(pdp_response_valid[i])
-                ,   .mem_read(pdp_response_data[i])
+                ,   .mem_read_ready(cache_response_ready)
+                ,   .mem_read_valid(cache_response_valid)
+                ,   .mem_read(cache_response_data)
 
                 ,   .switch_df(0)
                 ,   .switch_if(0)
-- 
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