From c3dd0394c82716f1aeccda7042fbe9baec42aa22 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 15 May 2022 15:52:01 -0700
Subject: Only phase shift the RS232 tx clock when we are between bytes.

---
 hdl/top.sv | 5 +++++
 1 file changed, 5 insertions(+)

(limited to 'hdl/top.sv')

diff --git a/hdl/top.sv b/hdl/top.sv
index 2ee6be9..d7e6acc 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -52,6 +52,8 @@ module top
     bit rs232_rx_clock;
     assign rs232_rx_clock = internal_clock;
 
+    bit rs232_clock_busy;
+
     bit         wire_tx_ready;
     bit         wire_tx_valid;
     uart_byte_t wire_tx_data;
@@ -63,6 +65,8 @@ module top
         (   .clock(rs232_tx_clock)
         ,   .reset(rs232_tx_reset)
 
+        ,   .clock_busy(rs232_clock_busy)
+
         ,   .out_ready(wire_tx_ready)
         ,   .out_valid(wire_tx_valid)
         ,   .out_data(wire_tx_data)
@@ -102,6 +106,7 @@ module top
         (   .clock(rs232_rx_clock)
         ,   .reset(internal_reset)
 
+        ,   .clock_busy(rs232_clock_busy)
         ,   .clock_out(rs232_tx_clock)
 
         ,   .in_ready(wire_rx_ready)
-- 
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