From c9697a5bc6e315be8441223fbb07d00e57547e2f Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 15 May 2022 15:50:21 -0700
Subject: Consistent RS232 wire names (DCE side names is used everywhere)

---
 hdl/top.sv | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)

(limited to 'hdl/top.sv')

diff --git a/hdl/top.sv b/hdl/top.sv
index a58ff0e..2ee6be9 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -8,10 +8,10 @@ module top
     ,   inout   wire    [28:13] gpiob
     ,   inout   wire    [40:31] gpioc
 
-    ,   output  wire            rs232_tx
-    ,   input   wire            rs232_rx
-    ,   output  wire            rs232_rts
-    ,   input   wire            rs232_cts
+    ,   output  wire            rs232_rxd
+    ,   input   wire            rs232_txd
+    ,   output  wire            rs232_cts
+    ,   input   wire            rs232_rts
 
     ,   output  wire            debug_tx
     ,   output  wire            debug_rx
@@ -24,8 +24,8 @@ module top
     ,   inout   bit     [7:0]   ram_data
     );
 
-    assign debug_tx = rs232_tx;
-    assign debug_rx = rs232_rx;
+    assign debug_tx = rs232_rxd;
+    assign debug_rx = rs232_txd;
 
     bit internal_clock;
     bit internal_reset;
@@ -67,8 +67,8 @@ module top
         ,   .out_valid(wire_tx_valid)
         ,   .out_data(wire_tx_data)
 
-        ,   .tx(rs232_tx)
-        ,   .cts(rs232_cts)
+        ,   .rxd(rs232_rxd)
+        ,   .rts(rs232_rts)
         );
 
     bit         rs232_tx_ready;
@@ -108,8 +108,8 @@ module top
         ,   .in_valid(wire_rx_valid)
         ,   .in_data(wire_rx_data)
 
-        ,   .rx(rs232_rx)
-        ,   .rts(rs232_rts)
+        ,   .txd(rs232_txd)
+        ,   .cts(rs232_cts)
         );
 
     bit         rs232_rx_ready;
-- 
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