From fce46a9a7bb2fe2a9b3addca0f488931b9e231ff Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 13 Mar 2022 16:50:34 -0700
Subject: Add memory arbiter and broadcast in between command UART and DRAM.

---
 hdl/top.sv | 80 +++++++++++++++++++++++++++++++++++++++++++++++++-------------
 1 file changed, 63 insertions(+), 17 deletions(-)

(limited to 'hdl/top.sv')

diff --git a/hdl/top.sv b/hdl/top.sv
index 5c8b531..ba6311f 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -48,9 +48,25 @@ module top
     bit             command_valid;
     ram_command_t   command_data;
 
-    bit                 result_ready;
-    bit                 result_valid;
-    ram_read_response_t result_data;
+    bit             ram_command_ready;
+    bit             ram_command_valid;
+    ram_command_t   ram_command_data;
+
+    bit                 ram_response_ready;
+    bit                 ram_response_valid;
+    ram_read_response_t ram_response_data;
+
+    bit                 print_ready;
+    bit                 print_valid;
+    ram_read_response_t print_data;
+
+    bit             [`NUM_PDPS-1:0] pdp_command_ready;
+    bit             [`NUM_PDPS-1:0] pdp_command_valid;
+    pdp_command_t   [`NUM_PDPS-1:0] pdp_command_data;
+
+    bit                 [`NUM_PDPS-1:0] pdp_response_ready;
+    bit                 [`NUM_PDPS-1:0] pdp_response_valid;
+    pdp_read_response_t [`NUM_PDPS-1:0] pdp_response_data;
 
     bit         ram_rwds_oe;
     bit         ram_rwds_out;
@@ -78,7 +94,7 @@ module top
         ,   .t_ena(ram_rx_valid)
         );
 
-    echo_arbiter arb
+    echo_arbiter uart0arb
         (   .clock(internal_clock)
         ,   .reset(internal_reset)
 
@@ -95,9 +111,7 @@ module top
         ,   .out_data(ram_tx_data)
         );
 
-    command_parser
-        #(  .TAG(0)
-        ) parser
+    command_parser parser
         (   .clock(internal_clock)
         ,   .reset(internal_reset)
 
@@ -114,7 +128,7 @@ module top
         ,   .command_data(command_data)
         );
 
-    ram_controller ram
+    mem_arbiter memarb
         (   .clock(internal_clock)
         ,   .reset(internal_reset)
 
@@ -122,9 +136,26 @@ module top
         ,   .command_valid(command_valid)
         ,   .command_data(command_data)
 
-        ,   .result_ready(result_ready)
-        ,   .result_valid(result_valid)
-        ,   .result_data(result_data)
+        ,   .pdp_ready(pdp_command_ready)
+        ,   .pdp_valid(pdp_command_valid)
+        ,   .pdp_data(pdp_command_data)
+
+        ,   .ram_ready(ram_command_ready)
+        ,   .ram_valid(ram_command_valid)
+        ,   .ram_data(ram_command_data)
+        );
+
+    ram_controller ram
+        (   .clock(internal_clock)
+        ,   .reset(internal_reset)
+
+        ,   .command_ready(ram_command_ready)
+        ,   .command_valid(ram_command_valid)
+        ,   .command_data(ram_command_data)
+
+        ,   .result_ready(ram_response_ready)
+        ,   .result_valid(ram_response_valid)
+        ,   .result_data(ram_response_data)
 
         ,   .ram_resetn(ram_resetn)
         ,   .ram_csn(ram_csn)
@@ -138,15 +169,30 @@ module top
         ,   .ram_data_out(ram_data_out)
         );
 
-    result_printer
-        #(  .TAG(0)
-        ) print
+    mem_broadcast memcast
+        (   .clock(internal_clock)
+        ,   .reset(internal_reset)
+
+        ,   .ram_ready(ram_response_ready)
+        ,   .ram_valid(ram_response_valid)
+        ,   .ram_data(ram_response_data)
+
+        ,   .print_ready(print_ready)
+        ,   .print_valid(print_valid)
+        ,   .print_data(print_data)
+
+        ,   .pdp_ready(pdp_response_ready)
+        ,   .pdp_valid(pdp_response_valid)
+        ,   .pdp_data(pdp_response_data)
+        );
+
+    result_printer print
         (   .clock(internal_clock)
         ,   .reset(internal_reset)
 
-        ,   .result_ready(result_ready)
-        ,   .result_valid(result_valid)
-        ,   .result_data(result_data)
+        ,   .result_ready(print_ready)
+        ,   .result_valid(print_valid)
+        ,   .result_data(print_data)
 
         ,   .echo_ready(ram_echo_in1_ready)
         ,   .echo_valid(ram_echo_in1_valid)
-- 
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