From 08a154de3bc7df73115a860a35db2173abfde9a3 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Fri, 18 Mar 2022 08:59:41 -0700
Subject: Minor paranoia about ensuring that we're in the correct half_state
 coming out of t_rwr delay between memory transactions

---
 hdl/ram_controller.sv | 1 +
 1 file changed, 1 insertion(+)

(limited to 'hdl')

diff --git a/hdl/ram_controller.sv b/hdl/ram_controller.sv
index 8922a09..14a1609 100644
--- a/hdl/ram_controller.sv
+++ b/hdl/ram_controller.sv
@@ -129,6 +129,7 @@ module ram_controller
                 ram_data_oe = 0;
                 ram_csn = 1;
                 ram_clkp = 0;
+                half_state = half_state.first;
                 if (trwr_counter != 0) --trwr_counter;
             end else if (half_state == TOGGLE_CLOCK) begin
                 half_state = half_state.next;
-- 
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