From 218fccd59b9750c87907917de245d3b72a518768 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Fri, 22 Apr 2022 22:54:26 -0700
Subject: Asynchronous reset on RS232 uart.

---
 hdl/rs232.sv | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

(limited to 'hdl')

diff --git a/hdl/rs232.sv b/hdl/rs232.sv
index 420f273..9050464 100644
--- a/hdl/rs232.sv
+++ b/hdl/rs232.sv
@@ -25,7 +25,7 @@ module rs232_tx
 
     bit [$clog2(`UART_BYTE_BITS):0] data_bits;
 
-    always @(posedge clock) begin
+    always @(posedge clock, posedge reset) begin
         if (reset) begin
             out_ready = 0;
             tx = 1;
@@ -108,7 +108,7 @@ module rs232_rx
     bit         [$clog2(`UART_BYTE_BITS):0] data_bits;
     bit                                     parity;
 
-    always @(posedge clock) begin
+    always @(posedge clock, posedge reset) begin
         if (reset) begin
             in_valid = 0;
             state = state.first;
-- 
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