From 593d29862d285987fd60ac18a90f8e5455f9fdc1 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 27 Mar 2022 16:59:18 -0700
Subject: Add a clock output pin for debugging the PLL.

---
 hdl/top.sv | 3 +++
 1 file changed, 3 insertions(+)

(limited to 'hdl')

diff --git a/hdl/top.sv b/hdl/top.sv
index 38ab638..dcf04b5 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -7,6 +7,7 @@ module top
     ,   inout   wire    [10:1]  gpioa
     ,   inout   wire    [28:13] gpiob
     ,   inout   wire    [40:31] gpioc
+    ,   output  wire            clock_out
 
     ,   output  bit             ram_resetn
     ,   output  bit             ram_csn
@@ -28,6 +29,8 @@ module top
         ,   .reset(internal_reset)
         );
 
+    assign clock_out = internal_clock;
+
     bit         ram_rx_ready;
     bit         ram_rx_valid;
     uart_byte_t ram_rx_data;
-- 
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