From 716ed41a46aea2a3c81564b6e6a55e3b3e43ec46 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Sun, 15 May 2022 15:53:36 -0700
Subject: Fix the RS232 receive state machine 😠💢:mad:

Our current consensus is that we have a bug which causes the RX state
machine to make incomprehensible jumps when the sample counter is more
than about 9 bits wide. We haven't completely pinned down the problem;
we saw it when running at 1Mbaud with a 7 bit (one extra bit) counter.

I hate Verilog and Altera, both exclusively and in combination.
---
 hdl/rs232.sv | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

(limited to 'hdl')

diff --git a/hdl/rs232.sv b/hdl/rs232.sv
index 2a31e31..29ccb6c 100644
--- a/hdl/rs232.sv
+++ b/hdl/rs232.sv
@@ -136,7 +136,7 @@ module rs232_rx
     bit         [$clog2(`UART_BYTE_BITS):0] data_bits;
     bit                                     parity;
 
-    bit         [$clog2(OVERSAMPLE+1)+2:0]  sample;
+    bit         [$clog2(OVERSAMPLE+1):0]    sample;
     bit         [$clog2(OVERSAMPLE+1):0]    clock_counter;
     bit         [$clog2(OVERSAMPLE+1):0]    next_clock_counter;
 
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