From 8dd900cb724d7d47560414d17f1be440817a0bd1 Mon Sep 17 00:00:00 2001
From: Julian Blake Kongslie
Date: Fri, 22 Apr 2022 22:54:57 -0700
Subject: Oversample RS232 RX uart.

---
 hdl/rs232.sv | 79 +++++++++++++++++++++++++++++++++++++-----------------------
 hdl/top.sv   | 40 +++++++++++++++++++++---------
 2 files changed, 77 insertions(+), 42 deletions(-)

(limited to 'hdl')

diff --git a/hdl/rs232.sv b/hdl/rs232.sv
index 9050464..31beb1e 100644
--- a/hdl/rs232.sv
+++ b/hdl/rs232.sv
@@ -87,6 +87,8 @@ module rs232_tx
 endmodule
 
 module rs232_rx
+    #(  OVERSAMPLE = 0
+    )
     (   input   bit         clock
     ,   input   bit         reset
 
@@ -108,6 +110,8 @@ module rs232_rx
     bit         [$clog2(`UART_BYTE_BITS):0] data_bits;
     bit                                     parity;
 
+    bit         [$clog2(OVERSAMPLE+1):0]    sample;
+
     always @(posedge clock, posedge reset) begin
         if (reset) begin
             in_valid = 0;
@@ -115,47 +119,62 @@ module rs232_rx
             buffer = 0;
             data_bits = 0;
             parity = 0;
+            sample = 0;
         end else begin
+            automatic bit ok = 0;
+
             if (in_ready && in_valid)
                 in_valid = 0;
 
-            case (state)
+            if (state == state.first) begin
+                ok = 1;
+            end else begin
+                ++sample;
+                if (sample == OVERSAMPLE+1) begin
+                    sample = 0;
+                    ok = 1;
+                end
+            end
+
+            if (ok) begin
+                case (state)
 
-                START: begin
-                    if (rx == 0) begin
-                        state = state.next;
-                        buffer = 0;
-                        data_bits = 0;
-                        parity = 0;
+                    START: begin
+                        if (rx == 0) begin
+                            state = state.next;
+                            buffer = 0;
+                            data_bits = 0;
+                            parity = 0;
+                        end
                     end
-                end
 
-                DATA: begin
-                    buffer[data_bits] = rx;
-                    parity = parity ^ rx;
-                    if (data_bits == `UART_BYTE_BITS-1)
-                        state = state.next;
-                    else
-                        ++data_bits;
-                end
+                    DATA: begin
+                        buffer[data_bits] = rx;
+                        parity = parity ^ rx;
+                        if (data_bits == `UART_BYTE_BITS-1)
+                            state = state.next;
+                        else
+                            ++data_bits;
+                    end
 
-                PARITY: begin
-                    parity = parity ^ rx;
-                    if (parity == 0)
-                        state = state.next;
-                    else
-                        state = state.first;
-                end
+                    PARITY: begin
+                        parity = parity ^ rx;
+                        if (parity == 0)
+                            state = state.next;
+                        else
+                            state = state.first;
+                    end
 
-                STOP: begin
-                    if (!in_valid && rx == 1) begin
-                        in_valid = 1;
-                        in_data = buffer;
+                    STOP: begin
+                        if (!in_valid && rx == 1) begin
+                            in_valid = 1;
+                            in_data = buffer;
+                        end
+                        state = state.next;
                     end
-                    state = state.next;
-                end
 
-            endcase
+                endcase
+            end
         end
     end
 
diff --git a/hdl/top.sv b/hdl/top.sv
index ca45aa9..ffe6656 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -34,28 +34,42 @@ module top
 
     //assign clock_out = internal_clock;
 
-    bit rs232_clock = 0;
-    bit [17:0] rs232_div = 0;
+    bit rs232_tx_clock = 0;
+    bit [17:0] rs232_tx_div = 0;
     always @(posedge internal_clock) begin
         if (internal_reset) begin
-            rs232_clock = 0;
-            rs232_div = 0;
+            rs232_tx_clock = 0;
+            rs232_tx_div = 0;
         end else begin
-            if (++rs232_div == 49987) begin // (30MHz/2)/300
-                ++rs232_clock;
-                rs232_div = 0;
+            if (++rs232_tx_div == 130) begin // (30MHz/2)/115200
+                ++rs232_tx_clock;
+                rs232_tx_div = 0;
             end
         end
     end
 
-    assign clock_out = rs232_clock;
+    assign clock_out = rs232_tx_clock;
+
+    bit rs232_rx_clock = 0;
+    bit [4:0] rs232_rx_div = 0;
+    always @(posedge internal_clock) begin
+        if (internal_reset) begin
+            rs232_rx_clock = 0;
+            rs232_rx_div = 0;
+        end else begin
+            if (++rs232_rx_div == 16) begin // (30MHz/2)/(115200*8)
+                ++rs232_rx_clock;
+                rs232_rx_div = 0;
+            end
+        end
+    end
 
     bit         wire_tx_ready;
     bit         wire_tx_valid;
     uart_byte_t wire_tx_data;
 
     rs232_tx wiretx
-        (   .clock(rs232_clock)
+        (   .clock(rs232_tx_clock)
         ,   .reset(internal_reset)
 
         ,   .out_ready(wire_tx_ready)
@@ -73,7 +87,7 @@ module top
         #(  .WIDTH_BITS($bits(uart_byte_t))
         ) fifotx
         (   .clock_in(internal_clock)
-        ,   .clock_out(rs232_clock)
+        ,   .clock_out(rs232_tx_clock)
 
         ,   .in_ready(rs232_tx_ready)
         ,   .in_valid(rs232_tx_valid)
@@ -88,8 +102,10 @@ module top
     bit         wire_rx_valid;
     uart_byte_t wire_rx_data;
 
-    rs232_rx wirerx
-        (   .clock(rs232_clock)
+    rs232_rx
+        #(  .OVERSAMPLE(7)
+        ) wirerx
+        (   .clock(rs232_rx_clock)
         ,   .reset(internal_reset)
 
         ,   .in_ready(wire_rx_ready)
-- 
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