1. add pdp-8 unified cache that works with SMC
2. pipelining that works with SMC / start working on minhdl version of the core
3. write an SPI or I2C master on the FPGA to sample analog inputs
4. add global shared cache
5. ethernet
∞. fix hello.pal (in noncpu)

   Command block:

             +--------------+   +----------------+
       +-----| Echo Arbiter |<--| Result Printer |<-------------------------------+
       |     +--------------+   +----------------+                                |
       |       ^                                                                  |
       v       |                                                                  |
+--------+   +----------------+                                                   |
| UART 0 |-->| Command Parser |------------+   RAM block:                         |
+--------+   +----------------+            |                                      |
                                           |               +----------------+     |
                                           |               | Off-chip DRAM  |     |
                                           |               +----------------+     |
   PDP-8 block:                            |                 ^           |        |
                                           |                 |           v        |
+--------+   +-------+                     |               +----------------+     |
| UART 1 |<->| PDP-8 |                     v               | RAM Controller |     |
+--------+   +-------+                   +-------------+   +----------------+   +---------------+
             | Cache |------------------>| Mem Arbiter |-->| Another Cache  |-->| Mem Broadcast |
             +-------+                   +-------------+   +----------------+   +---------------+
                   ^                       ^                                      | |
                   |                       |                                      | |
                   +--------------------------------------------------------------+ |
                                           |                                        |
           *                               |                                        |
           * (PDP-8s are replicated)       |                                        |
           *                               |                                        |
                                           |                                        |
+--------+   +-------+                     |                                        |
| UART N |<->| PDP-8 |                     |                                        |
+--------+   +-------+                     |                                        |
             | Cache |---------------------+                                        |
             +-------+                                                              |
                   ^                                                                |
                   |                                                                |
                   +----------------------------------------------------------------+

    Echo Arbiter:  Trivial priority arbiter (input echo has priority over the result printer)
    Nen Arbiter:   Adds clog2(1 + number of PDP-8s) tag bits indicating which channel was selected
                   For inputs coming from a PDP-8 as opposed to the command parser, add the appropriate prefix to the memory address
    Mem Broadcast: Removes clog2(1 + number of PDP-8s) tag bits to determine which channel to send to
                   For outputs going to a PDP-8 as opposed to the result printer, strip excess address bits

Note that the mem arbiter and broadcast have to be as wide as (number of
PDP-8s)+1, so they will wind up being bottlenecks. The memory protocol allows
arbitrary stalls, so multi-cycle arbitration is possible.

Not shown is the front panel interface.