module fifo #( WIDTH_BITS = 1 , DEPTH_BITS = 10 ) ( input bit clock_in , input bit clock_out , input bit reset , output bit in_ready , input bit in_valid , input bit [WIDTH_BITS-1:0] in_data , input bit out_ready , output bit out_valid , output bit [WIDTH_BITS-1:0] out_data ); localparam DEPTH = 1<> 1); in_ready = oldest_plus_one_wrap_grey != youngest_grey; end end always @(posedge clock_out, posedge reset) begin if (reset) begin out_valid = 0; oldest = 0; oldest_wrap = 0; oldest_grey = 0; oldest_plus_one_wrap_grey = {!oldest_wrap, oldest} ^ ({!oldest_wrap, oldest} >> 1); end else begin if (out_ready && out_valid) begin if (++oldest == 0) ++oldest_wrap; end oldest_grey = {oldest_grey, oldest} ^ ({oldest_grey, oldest} >> 1); oldest_plus_one_wrap_grey = {!oldest_wrap, oldest} ^ ({!oldest_wrap, oldest} >> 1); out_valid = oldest_grey != youngest_grey; out_data = data[oldest]; end end endmodule