noncpu/hdl/mem.sv, branch main

noncpu/hdl/mem.sv, branch main Unnamed repository; edit this file 'description' to name the repository. https://git.jblake.org/noncpu/atom?h=main 2021-04-08T00:02:03Z Switch back to $past-based scheduling; my clever idea wasn't clever enough. 2021-04-08T00:02:03Z Julian Blake Kongslie 2021-04-08T00:02:03Z urn:sha1:238a43e587bfbe6574d34ef36553619249797260 Change our simulator timing model to use continuous assignment guards. 2021-04-05T17:20:02Z Julian Blake Kongslie 2021-04-05T17:20:02Z urn:sha1:6a1c04608090cc8fc88aafac0b4899e4cbb9cae9 Instead of depending on verilator getting $past right, this (ab-)uses the SystemVerilog scheduling model which allows us to get a consistent view of the universe by "isolating" the blocking updates. Easier to code to and seems to be more reliable in verilator. Yet another lame attempt. 2021-03-29T00:19:12Z Julian Blake Kongslie 2021-03-29T00:19:12Z urn:sha1:0c9e672cffa935f4db57d99e161a0c22b2b25cd9 Use a separate memory module. 2021-03-28T23:32:13Z Julian Blake Kongslie 2021-03-28T23:32:13Z urn:sha1:9d5484923941eb393381b5769a4f1f66ff5df5ca Hopefully this will infer a memory the way we want in Quartus.