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<title>noncpu/hdl/top.sv, branch wip</title>
<subtitle>Unnamed repository; edit this file 'description' to name the repository.
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<updated>2021-04-18T21:46:30Z</updated>
<entry>
<title>Move the core logic out of the top module.</title>
<updated>2021-04-18T21:46:30Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2021-04-18T21:46:30Z</published>
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<content type='text'>
</content>
</entry>
<entry>
<title>Change synthesis of PLL wrapper to avoid latch logic.</title>
<updated>2021-04-15T23:39:58Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2021-04-15T23:39:58Z</published>
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<id>urn:sha1:abd9703a1b96225db0d7317bf8833467150bae26</id>
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</entry>
<entry>
<title>Use internal PLL for clock and reset generation.</title>
<updated>2021-04-15T01:24:34Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2021-04-14T15:44:31Z</published>
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<id>urn:sha1:3975a7e26d0ad8c7f33e28e1222d1e09f7bcdb82</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Add UART receive opbit.</title>
<updated>2021-04-08T00:02:31Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2021-04-08T00:02:31Z</published>
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<id>urn:sha1:196b67bba9fcb8d8752311f4cf461c82c3d62efb</id>
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</content>
</entry>
<entry>
<title>Switch back to $past-based scheduling; my clever idea wasn't clever enough.</title>
<updated>2021-04-08T00:02:03Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2021-04-08T00:02:03Z</published>
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<id>urn:sha1:238a43e587bfbe6574d34ef36553619249797260</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Change the null byte from no-op to halt.</title>
<updated>2021-04-05T20:32:41Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2021-04-05T20:32:41Z</published>
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<id>urn:sha1:8c0b7ea39d57cb6c80cf66207291837d95c71940</id>
<content type='text'>
</content>
</entry>
<entry>
<title>Change our simulator timing model to use continuous assignment guards.</title>
<updated>2021-04-05T17:20:02Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2021-04-05T17:20:02Z</published>
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<id>urn:sha1:6a1c04608090cc8fc88aafac0b4899e4cbb9cae9</id>
<content type='text'>
Instead of depending on verilator getting $past right, this (ab-)uses
the SystemVerilog scheduling model which allows us to get a consistent
view of the universe by "isolating" the blocking updates. Easier to code
to and seems to be more reliable in verilator.
</content>
</entry>
<entry>
<title>Make PC ADDR-sized rather than DATA-sized for now</title>
<updated>2021-04-05T17:19:01Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2021-04-05T17:19:01Z</published>
<link rel='alternate' type='text/html' href='https://git.jblake.org/noncpu/commit/?id=0bf6ec12c73e9f037de6b35bb08d94dfe9c6045c'/>
<id>urn:sha1:0bf6ec12c73e9f037de6b35bb08d94dfe9c6045c</id>
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</content>
</entry>
<entry>
<title>Remove some old debug messages.</title>
<updated>2021-04-05T17:16:58Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2021-04-05T17:16:58Z</published>
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<id>urn:sha1:5d3d64d703fd8c1ef94bd3b67a2e3e43414df604</id>
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</content>
</entry>
<entry>
<title>Remove idx, add indirect jumps, renumber opcodes so NOP=0, add absolute labels to asm.rb</title>
<updated>2021-04-04T23:20:24Z</updated>
<author>
<name>Julian Blake Kongslie</name>
</author>
<published>2021-04-04T23:20:24Z</published>
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