Change our simulator timing model to use continuous assignment guards.

Instead of depending on verilator getting $past right, this (ab-)uses
the SystemVerilog scheduling model which allows us to get a consistent
view of the universe by "isolating" the blocking updates. Easier to code
to and seems to be more reliable in verilator.

4 files changed, 113 insertions, 86 deletions

diff --git a/hdl/jtag_uart.sv b/hdl/jtag_uart.sv
index ad4665e..2b5f334 100644
--- a/hdl/jtag_uart.sv
+++ b/hdl/jtag_uart.sv
@@ -9,15 +9,22 @@ module jtag_uart
     (   input   bit clk
     ,   input   bit reset
 
-    ,   input   bit         rx_ready    `define rx_ready `past(rx_ready)
+    ,   input   bit         rx_ready
     ,   output  bit         rx_valid
     ,   output  bit [7:0]   rx_data
 
     ,   output  bit         tx_ready
-    ,   input   bit         tx_valid    `define tx_valid `past(tx_valid)
-    ,   input   bit [7:0]   tx_data     `define tx_data `past(tx_data)
+    ,   input   bit         tx_valid
+    ,   input   bit [7:0]   tx_data
     );
 
+`input(rx_ready)
+`output(rx_valid)
+`output(rx_data)
+`output(tx_ready)
+`input(tx_valid)
+`input(tx_data)
+
 `ifdef SYNTHESIS
 
 alt_jtag_atlantic
@@ -28,12 +35,12 @@ alt_jtag_atlantic
     ) real_jtag
     (   .clk(clk)
     ,   .rst_n(!reset)
-    ,   .r_dat(tx_data)
-    ,   .r_val(tx_valid)
-    ,   .r_ena(tx_ready)
-    ,   .t_dat(rx_data)
-    ,   .t_dav(rx_ready)
-    ,   .t_ena(rx_valid)
+    ,   .r_dat(tx_data_)
+    ,   .r_val(tx_valid_)
+    ,   .r_ena(tx_ready_)
+    ,   .t_dat(rx_data_)
+    ,   .t_dav(rx_ready_)
+    ,   .t_ena(rx_valid_)
     );
 
 `else
@@ -48,34 +55,34 @@ bit [7:0] tx_b_data;
 
 always_ff @(posedge clk) begin
     if (reset) begin
-        rx_valid = 0;
-        tx_ready = 0;
+        rx_valid_ = 0;
+        tx_ready_ = 0;
         sim_rx_addr = 0;
         tx_b_valid = 0;
     end else begin
         automatic bit [7:0] sim_rx_data = sim_rx_rom[sim_rx_addr];
 
         // RX logic
-        if (`rx_ready) rx_valid = 0;
-        if (!rx_valid && (sim_rx_data != 0)) begin
+        if (rx_ready_) rx_valid_ = 0;
+        if (!rx_valid_ && (sim_rx_data != 0)) begin
 `ifdef JTAG_UART_LOCAL_ECHO
             $write("%s", sim_rx_data);
 `endif
-            rx_valid = 1;
-            rx_data = sim_rx_data;
+            rx_valid_ = 1;
+            rx_data_ = sim_rx_data;
             ++sim_rx_addr;
         end
 
         // TX logic
-        if (tx_ready && `tx_valid) begin
+        if (tx_ready_ && tx_valid_) begin
             tx_b_valid = 1;
-            tx_b_data = `tx_data;
+            tx_b_data = tx_data_;
         end
         if (tx_b_valid) begin
             $write("%s", tx_b_data);
             tx_b_valid = 0;
         end
-        tx_ready = !tx_b_valid;
+        tx_ready_ = !tx_b_valid;
     end
 end
 
diff --git a/hdl/mem.sv b/hdl/mem.sv
index 9be5c4d..c362e37 100644
--- a/hdl/mem.sv
+++ b/hdl/mem.sv
@@ -5,10 +5,10 @@ module mem
     ,   input   bit reset
 
     ,   output  bit                 ready
-    ,   input   bit                 valid       `define valid `past(valid)
-    ,   input   bit                 write       `define write `past(write)
-    ,   input   bit [ADDR_BITS-1:0] address     `define address `past(address)
-    ,   input   bit [DATA_BITS-1:0] write_data  `define write_data `past(write_data)
+    ,   input   bit                 valid
+    ,   input   bit                 write
+    ,   input   bit [ADDR_BITS-1:0] address
+    ,   input   bit [DATA_BITS-1:0] write_data
 
     ,   output  bit                 read_valid
     ,   output  bit [DATA_BITS-1:0] read_data
@@ -18,24 +18,32 @@ parameter ADDR_BITS;
 parameter DATA_BITS;
 parameter INIT_FILE;
 
+`output(ready)
+`input(valid)
+`input(write)
+`input(address)
+`input(write_data)
+`output(read_valid)
+`output(read_data)
+
 bit [DATA_BITS-1:0] storage [0:(1<<ADDR_BITS)-1];
 initial $readmemh(INIT_FILE, storage);
 
 always_ff @(posedge clk) begin
     if (reset) begin
-        ready = 0;
-        read_valid = 0;
+        ready_ = 0;
+        read_valid_ = 0;
     end else begin
-        read_valid = 0;
-        if (ready && `valid) begin
-            if (`write) begin
-                storage[`address] = `write_data;
+        read_valid_ = 0;
+        if (ready_ && valid_) begin
+            if (write_) begin
+                storage[address_] = write_data_;
             end else begin
-                read_valid = 1;
-                read_data = storage[`address];
+                read_valid_ = 1;
+                read_data_ = storage[address_];
             end
         end
-        ready = 1;
+        ready_ = 1;
     end
 end
 
diff --git a/hdl/top.sv b/hdl/top.sv
index 34b9769..54cfdc5 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -13,14 +13,14 @@ bit have_reset = 0;
 always_ff @(posedge clk) if (reset) have_reset <= 1;
 assign reset = !reset_n || !have_reset;
 
-bit mem_ready; `define mem_ready `past(mem_ready)
+bit mem_ready;
 bit mem_valid;
 bit mem_write;
 bit [ADDR_BITS-1:0] mem_address;
 bit [DATA_BITS-1:0] mem_write_data;
 
-bit mem_read_valid; `define mem_read_valid `past(mem_read_valid)
-bit [DATA_BITS-1:0] mem_read_data; `define mem_read_data `past(mem_read_data)
+bit mem_read_valid;
+bit [DATA_BITS-1:0] mem_read_data;
 
 mem
     #(  .ADDR_BITS(ADDR_BITS)
@@ -41,6 +41,14 @@ mem
     ,   .read_data(mem_read_data)
     );
 
+`input(mem_ready)
+`output(mem_valid)
+`output(mem_address)
+`output(mem_write)
+`output(mem_write_data)
+`input(mem_read_valid)
+`input(mem_read_data)
+
 bit rx_ready;
 bit rx_valid;
 bit [7:0] rx_data;
@@ -56,14 +64,21 @@ jtag_uart
     ,   .reset(reset)
 
     ,   .rx_ready(rx_ready)
-    ,   .rx_valid(rx_valid) `define rx_valid `past(rx_valid)
-    ,   .rx_data(rx_data)   `define rx_data `past(rx_data)
+    ,   .rx_valid(rx_valid)
+    ,   .rx_data(rx_data)
 
-    ,   .tx_ready(tx_ready) `define tx_ready `past(tx_ready)
+    ,   .tx_ready(tx_ready)
     ,   .tx_valid(tx_valid)
     ,   .tx_data(tx_data)
     );
 
+`output(rx_ready)
+`input(rx_valid)
+`input(rx_data)
+`input(tx_ready)
+`output(tx_valid)
+`output(tx_data)
+
 bit [ADDR_BITS-1:0] pc;
 bit [3:0] opcode;
 bit [7:0] operand;
@@ -84,33 +99,33 @@ enum
 
 always_ff @(posedge clk) begin
     if (reset) begin
-        mem_valid = 0;
-        rx_ready = 0;
-        tx_valid = 0;
-        tx_data = 0;
+        mem_valid_ = 0;
+        rx_ready_ = 0;
+        tx_valid_ = 0;
+        tx_data_ = 0;
         pc = 0;
         acc = 0;
         state = state.first;
     end else begin
-        if (`tx_ready) tx_valid = 0;
+        if (tx_ready_) tx_valid_ = 0;
 
         case (state)
             FETCH: begin
-                mem_valid = 1;
+                mem_valid_ = 1;
                 mem_address_ = pc;
-                mem_write = 0;
-                if (`mem_ready) begin
+                mem_write_ = 0;
+                if (mem_ready_) begin
                     state = DECODE;
                     ++pc;
                 end
             end
 
             DECODE: begin
-                mem_valid = 0;
-                mem_write = 0;
-                if (`mem_read_valid) begin
+                mem_valid_ = 0;
+                mem_write_ = 0;
+                if (mem_read_valid_) begin
                     state = FETCH;
-                    {opcode, operand} = `mem_read_data;
+                    {opcode, operand} = mem_read_data_;
                     sign_extended_operand = {{(DATA_BITS-8){operand[7]}}, operand};
                     case (opcode)
                         'h0: begin
@@ -135,7 +150,7 @@ always_ff @(posedge clk) begin
                             end
                         end
                         'h6: begin
-                            mem_write_data = acc % 10 + 'h30;
+                            mem_write_data_ = acc % 10 + 'h30;
                             acc = acc / 10;
                             address = {7'b0, operand[6:0]};
                             state = operand[7] ? INDIRECT : AGEN;
@@ -145,70 +160,70 @@ always_ff @(posedge clk) begin
             end
 
             INDIRECT: begin
-                mem_valid = 1;
-                mem_write = 0;
-                mem_address = address;
-                state = `mem_ready ? INDIRECTED : INDIRECT;
+                mem_valid_ = 1;
+                mem_write_ = 0;
+                mem_address_ = address;
+                state = mem_ready_ ? INDIRECTED : INDIRECT;
             end
 
             INDIRECTED: begin
-                if (`mem_ready) begin
-                    mem_valid = 0;
-                    mem_write = 0;
+                if (mem_ready_) begin
+                    mem_valid_ = 0;
+                    mem_write_ = 0;
                 end
-                if (`mem_read_valid) begin
-                    address = {{(ADDR_BITS - DATA_BITS){1'b0}}, `mem_read_data};
+                if (mem_read_valid_) begin
+                    address = {{(ADDR_BITS - DATA_BITS){1'b0}}, mem_read_data_};
                     state = AGEN;
                 end
             end
 
             AGEN: begin
-                mem_valid = 0;
-                mem_write = 0;
+                mem_valid_ = 0;
+                mem_write_ = 0;
                 state = FETCH;
                 case (opcode)
                     'h2: begin
-                        mem_valid = 1;
-                        mem_address = address;
-                        state = `mem_ready ? MEMORY : AGEN;
+                        mem_valid_ = 1;
+                        mem_address_ = address;
+                        state = mem_ready_ ? MEMORY : AGEN;
                     end
                     'h3: begin
-                        mem_valid = 1;
-                        mem_address = address;
-                        mem_write = 1;
-                        mem_write_data = acc;
-                        state = `mem_ready ? FETCH : AGEN;
+                        mem_valid_ = 1;
+                        mem_address_ = address;
+                        mem_write_ = 1;
+                        mem_write_data_ = acc;
+                        state = mem_ready_ ? FETCH : AGEN;
                     end
                     'h5: pc = address;
                     'h6: begin
-                        mem_valid = 1;
-                        mem_address = address;
-                        mem_write = 1;
-                        state = `mem_ready ? FETCH : AGEN;
+                        mem_valid_ = 1;
+                        mem_address_ = address;
+                        mem_write_ = 1;
+                        state = mem_ready_ ? FETCH : AGEN;
                     end
                 endcase
             end
 
             MEMORY: begin
-                if (`mem_ready) begin
-                    mem_valid = 0;
-                    mem_write = 0;
+                if (mem_ready_) begin
+                    mem_valid_ = 0;
+                    mem_write_ = 0;
                 end
                 state = FETCH;
                 case (opcode)
                     'h0: begin
                         if (operand[6]) begin
-                            if (tx_valid) begin
+                            if (tx_valid_) begin
                                 state = MEMORY;
                             end else begin
-                                tx_valid = 1;
-                                tx_data = acc[7:0];
+                                tx_valid_ = 1;
+                                tx_data_ = acc[7:0];
                             end
                         end
                     end
                     'h2: begin
-                        if (`mem_read_valid) begin
-                            acc = acc + `mem_read_data;
+                        if (mem_read_valid_) begin
+                            acc = acc + mem_read_data_;
                         end else begin
                             state = MEMORY;
                         end
diff --git a/hdl/util.svh b/hdl/util.svh
index db5e4e6..fa6ddc5 100644
--- a/hdl/util.svh
+++ b/hdl/util.svh
@@ -1,5 +1,2 @@
-`ifdef SYNTHESIS
-`define past(x) x
-`else
-`define past(x) $sampled(x)
-`endif
+`define input(x) type(x) x``_; assign x``_ = x;
+`define output(x) type(x) x``_; assign x = x``_;