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| author | Julian Blake Kongslie | 2021-03-29 12:36:51 -0700 |
|---|---|---|
| committer | Julian Blake Kongslie | 2021-03-29 12:36:51 -0700 |
| commit | f48faf6598701a9d843e7b8d46a7ddf1bbe790c9 (patch) | |
| tree | 222fa343adafbc208c84224c9db99e3265ce69a0 | |
| parent | Vastly improve the edit-rebuild-debug cycle. (diff) | |
| download | noncpu-f48faf6598701a9d843e7b8d46a7ddf1bbe790c9.tar.xz | |
Fix WIDTH warnings from verilator.
| -rw-r--r-- | Makefile | 2 | ||||
| -rw-r--r-- | hdl/top.sv | 13 |
2 files changed, 9 insertions, 6 deletions
| @@ -9,7 +9,7 @@ sim: build/Vtop | |||
| 9 | 9 | ||
| 10 | build/Vtop: $(SOURCES) $(COLLATERAL) | 10 | build/Vtop: $(SOURCES) $(COLLATERAL) |
| 11 | @mkdir -p build | 11 | @mkdir -p build |
| 12 | verilator +1800-2017ext+sv -Wall -Wno-BLKSEQ -Wno-UNUSED -Wno-WIDTH -O3 -Ihdl $(OPTS) --Mdir build --trace --cc --build -j --exe --top-module top $(SOURCES) | 12 | verilator +1800-2017ext+sv -Wall -Wno-BLKSEQ -Wno-UNUSED -O3 -Ihdl $(OPTS) --Mdir build --trace --cc --build -j --exe --top-module top $(SOURCES) |
| 13 | 13 | ||
| 14 | clean: | 14 | clean: |
| 15 | rm -rf build | 15 | rm -rf build |
| @@ -70,6 +70,8 @@ bit [7:0] operand; | |||
| 70 | bit [DATA_BITS-1:0] acc; | 70 | bit [DATA_BITS-1:0] acc; |
| 71 | bit [DATA_BITS-1:0] idx; | 71 | bit [DATA_BITS-1:0] idx; |
| 72 | 72 | ||
| 73 | bit [DATA_BITS-1:0] sign_extended_operand; | ||
| 74 | |||
| 73 | enum | 75 | enum |
| 74 | { FETCH | 76 | { FETCH |
| 75 | , DECODE | 77 | , DECODE |
| @@ -110,13 +112,14 @@ always_ff @(posedge clk) begin | |||
| 110 | if (mem_read_valid) begin | 112 | if (mem_read_valid) begin |
| 111 | state = FETCH; | 113 | state = FETCH; |
| 112 | {opcode, operand} = mem_read_data; | 114 | {opcode, operand} = mem_read_data; |
| 115 | sign_extended_operand = {{(DATA_BITS-8){operand[7]}}, operand}; | ||
| 113 | `ifdef DEBUG $display("\tdecode %x:%x", opcode, operand); `endif | 116 | `ifdef DEBUG $display("\tdecode %x:%x", opcode, operand); `endif |
| 114 | case (opcode) | 117 | case (opcode) |
| 115 | 'h0: acc = {{4{operand[7]}}, operand}; | 118 | 'h0: acc = sign_extended_operand; |
| 116 | 'h1: state = AGEN; | 119 | 'h1: state = AGEN; |
| 117 | 'h2: state = AGEN; | 120 | 'h2: state = AGEN; |
| 118 | 'h3: if (acc != operand) ++pc; | 121 | 'h3: if (acc != sign_extended_operand) ++pc; |
| 119 | 'h4: pc = pc + {{4{operand[7]}}, operand}; | 122 | 'h4: pc = pc + sign_extended_operand; |
| 120 | 'hf: begin | 123 | 'hf: begin |
| 121 | if (operand[0]) ++acc; | 124 | if (operand[0]) ++acc; |
| 122 | if (operand[1]) --acc; | 125 | if (operand[1]) --acc; |
| @@ -139,12 +142,12 @@ always_ff @(posedge clk) begin | |||
| 139 | case (opcode) | 142 | case (opcode) |
| 140 | 'h1: begin | 143 | 'h1: begin |
| 141 | mem_valid = 1; | 144 | mem_valid = 1; |
| 142 | mem_address = idx + operand; | 145 | mem_address = {2'b0, idx + sign_extended_operand}; |
| 143 | state = mem_ready ? MEMORY : AGEN; | 146 | state = mem_ready ? MEMORY : AGEN; |
| 144 | end | 147 | end |
| 145 | 'h2: begin | 148 | 'h2: begin |
| 146 | mem_valid = 1; | 149 | mem_valid = 1; |
| 147 | mem_address = idx + operand; | 150 | mem_address = {2'b0, idx + sign_extended_operand}; |
| 148 | mem_write = 1; | 151 | mem_write = 1; |
| 149 | mem_write_data = acc; | 152 | mem_write_data = acc; |
| 150 | state = mem_ready ? FETCH : AGEN; | 153 | state = mem_ready ? FETCH : AGEN; |
