Change synthesis of PLL wrapper to avoid latch logic.pre-dp-8

2 files changed, 20 insertions, 32 deletions

diff --git a/hdl/clock.sv b/hdl/clock.sv
index b33645b..0a6633d 100644
--- a/hdl/clock.sv
+++ b/hdl/clock.sv
@@ -1,8 +1,8 @@
 `include "util.svh"
 
 module clock
-    #(  DIVIDE_BY   = 1
-    ,   MULTIPLY_BY = 1
+    #(  MULTIPLY_BY = 1
+    ,   DIVIDE_BY   = 1
     ,   NATIVE_PERIOD_PICOSECONDS = 20_000
     )
     (   input   bit native_clk
@@ -13,30 +13,26 @@ module clock
     );
 
 enum
-    {   AWAIT_LOCKED
-    ,   AWAIT_LOW
-    ,   AWAIT_HIGH
-    ,   AWAIT_LOW_2
+    {   NOT_LOCKED
+    ,   RESET_CYCLE
     ,   READY
     } state = state.first;
 
 bit locked;
 
-`ifdef SYNTHESIS
+`ifndef SYNTHESIS
+
+assign target_clk = native_clk;
+assign locked = 1;
+
+`else
 
 altpll
-    #(  .bandwidth_type("AUTO")
-    ,   .clk0_divide_by(DIVIDE_BY)
-    ,   .clk0_duty_cycle(50)
+    #(  .clk0_divide_by(DIVIDE_BY)
     ,   .clk0_multiply_by(MULTIPLY_BY)
-    ,   .clk0_phase_shift(0)
-    ,   .compensate_clock("CLK0")
     ,   .inclk0_input_frequency(NATIVE_PERIOD_PICOSECONDS)
     ,   .intended_device_family("Cyclone 10 LP")
-    ,   .lpm_hint("CBX_MODULE_PREFIX=clock")
-    ,   .lpm_type("altpll")
     ,   .operation_mode("NORMAL")
-    ,   .pll_type("AUTO")
     ,   .port_activeclock("PORT_UNUSED")
     ,   .port_areset("PORT_USED")
     ,   .port_clkbad0("PORT_UNUSED")
@@ -119,22 +115,14 @@ altpll
 
 `endif
 
-always_latch begin
-    `ifndef SYNTHESIS
-        target_clk = native_clk;
-        locked = 1;
-    `endif
-
-    if (!reset_n || !locked) state = AWAIT_LOCKED;
-
-    case (state)
-        AWAIT_LOCKED: if (locked) state = AWAIT_LOW;
-        AWAIT_LOW: if (!target_clk) state = AWAIT_HIGH;
-        AWAIT_HIGH: if (target_clk) state = AWAIT_LOW_2;
-        AWAIT_LOW_2: if (!target_clk) state = READY;
-    endcase
+always_ff @(posedge target_clk) begin
+    if (!reset_n || !locked) begin
+        state = state.first;
+    end else if (state != state.last) begin
+        state = state.next;
+    end
 
-    reset = !(state == READY);
+    reset = !(state == state.last);
 end
 
 endmodule
diff --git a/hdl/top.sv b/hdl/top.sv
index 46620cb..0aebd77 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -12,8 +12,8 @@ bit clk;
 bit reset;
 
 clock
-    #(  .DIVIDE_BY(10)
-    ,   .MULTIPLY_BY(9)
+    #(  .MULTIPLY_BY(9)
+    ,   .DIVIDE_BY(10)
     ) pll
     (   .native_clk(native_clk)
     ,   .reset_n(reset_n)