Yet another lame attempt.

2 files changed, 71 insertions, 34 deletions

diff --git a/hdl/mem.sv b/hdl/mem.sv
index 906870d..9be5c4d 100644
--- a/hdl/mem.sv
+++ b/hdl/mem.sv
@@ -1,12 +1,17 @@
+`include "util.svh"
+
 module mem
     (   input   bit clk
+    ,   input   bit reset
 
     ,   output  bit                 ready
-    ,   input   bit                 valid
-    ,   input   bit                 write
-    ,   input   bit [ADDR_BITS-1:0] address
-    ,   input   bit [DATA_BITS-1:0] write_data
-    ,   output  bit [DATA_BITS-1:0] read_data   // Valid exactly the cycle after address is consumed.
+    ,   input   bit                 valid       `define valid `past(valid)
+    ,   input   bit                 write       `define write `past(write)
+    ,   input   bit [ADDR_BITS-1:0] address     `define address `past(address)
+    ,   input   bit [DATA_BITS-1:0] write_data  `define write_data `past(write_data)
+
+    ,   output  bit                 read_valid
+    ,   output  bit [DATA_BITS-1:0] read_data
     );
 
 parameter ADDR_BITS;
@@ -16,14 +21,21 @@ parameter INIT_FILE;
 bit [DATA_BITS-1:0] storage [0:(1<<ADDR_BITS)-1];
 initial $readmemh(INIT_FILE, storage);
 
-assign ready = 1;
-
 always_ff @(posedge clk) begin
-    if (ready && valid) begin
-        if (write)
-            storage[address] <= write_data;
-        else
-            read_data <= storage[address];
+    if (reset) begin
+        ready = 0;
+        read_valid = 0;
+    end else begin
+        read_valid = 0;
+        if (ready && `valid) begin
+            if (`write) begin
+                storage[`address] = `write_data;
+            end else begin
+                read_valid = 1;
+                read_data = storage[`address];
+            end
+        end
+        ready = 1;
     end
 end
 
diff --git a/hdl/top.sv b/hdl/top.sv
index c87cc29..ac8342e 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -18,7 +18,9 @@ bit mem_valid;
 bit mem_write;
 bit [ADDR_BITS-1:0] mem_address;
 bit [DATA_BITS-1:0] mem_write_data;
-bit [DATA_BITS-1:0] mem_read_data;
+
+bit mem_read_valid; `define mem_read_valid `past(mem_read_valid)
+bit [DATA_BITS-1:0] mem_read_data; `define mem_read_data `past(mem_read_data)
 
 mem
     #(  .ADDR_BITS(ADDR_BITS)
@@ -27,12 +29,15 @@ mem
     )
     memory
     (   .clk(clk)
+    ,   .reset(reset)
 
     ,   .ready(mem_ready)
     ,   .valid(mem_valid)
     ,   .address(mem_address)
     ,   .write(mem_write)
     ,   .write_data(mem_write_data)
+
+    ,   .read_valid(mem_read_valid)
     ,   .read_data(mem_read_data)
     );
 
@@ -68,7 +73,9 @@ bit [DATA_BITS-1:0] idx;
 enum
     {   FETCH
     ,   DECODE
+    ,   AGEN
     ,   MEMORY
+    ,   HALT
     } state;
 
 always_ff @(posedge clk) begin
@@ -82,7 +89,7 @@ always_ff @(posedge clk) begin
         idx = 0;
         state = state.first;
     end else begin
-        `ifdef DEBUG $display("s=%0d pc=%x (acc=%x idx=%x)", state, pc, acc, idx); `endif
+        `ifdef DEBUG $display("s=%0d pc=%x (acc=%x idx=%x) (mem %b:%x)", state, pc, acc, idx, `mem_read_valid, `mem_read_data); `endif
         if (`tx_ready) tx_valid = 0;
 
         case (state)
@@ -98,51 +105,64 @@ always_ff @(posedge clk) begin
             end
 
             DECODE: begin
+                if (`mem_read_valid) begin
+                    mem_valid = 0;
+                    mem_write = 0;
+                    state = FETCH;
+                    {opcode, operand} = `mem_read_data;
+                    `ifdef DEBUG $display("\tdecode %x:%x", opcode, operand); `endif
+                    case (opcode)
+                        'h0: acc = {{4{operand[7]}}, operand};
+                        'h1: state = AGEN;
+                        'h2: state = AGEN;
+                        'h3: if (acc != operand) ++pc;
+                        'h4: pc = pc + {{4{operand[7]}}, operand};
+                        'hf: begin
+                            if (operand[0]) ++acc;
+                            if (operand[1]) --acc;
+                            if (operand[2]) ++idx;
+                            if (operand[3]) --idx;
+                            if (operand[4]) {idx, acc} = {acc, idx};
+                            if (operand[5]) idx = acc;
+                            if (operand[6]) state = MEMORY;
+                            if (operand[7]) state = HALT;
+                        end
+                    endcase
+                end
+            end
+
+            AGEN: begin
                 mem_valid = 0;
                 mem_write = 0;
                 state = FETCH;
-                {opcode, operand} = mem_read_data;
-                `ifdef DEBUG $display("\tdecode %x:%x", opcode, operand); `endif
+                `ifdef DEBUG $display("\tagen"); `endif
                 case (opcode)
-                    'h0: acc = {{4{operand[7]}}, operand};
                     'h1: begin
                         mem_valid = 1;
                         mem_address = idx + operand;
-                        state = MEMORY;
+                        state = `mem_ready ? MEMORY : AGEN;
                     end
                     'h2: begin
                         mem_valid = 1;
                         mem_address = idx + operand;
                         mem_write = 1;
                         mem_write_data = acc;
-                        if (! `mem_ready) state = MEMORY;
-                    end
-                    'h3: if (acc != operand) ++pc;
-                    'h4: pc = pc + {{4{operand[7]}}, operand};
-                    'hf: begin
-                        if (operand[0]) ++acc;
-                        if (operand[1]) --acc;
-                        if (operand[2]) ++idx;
-                        if (operand[3]) --idx;
-                        if (operand[4]) {idx, acc} = {acc, idx};
-                        if (operand[5]) idx = acc;
-                        if (operand[6]) state = MEMORY;
-                        if (operand[7]) state = DECODE;
+                        state = `mem_ready ? FETCH : AGEN;
                     end
                 endcase
             end
 
             MEMORY: begin
-                `ifdef DEBUG $display("\tstall"); `endif
                 if (`mem_ready) begin
                     mem_valid = 0;
                     mem_write = 0;
                 end
                 state = FETCH;
+                `ifdef DEBUG $display("\tstall"); `endif
                 case (opcode)
                     'h1: begin
-                        if (`mem_ready) begin
-                            acc = mem_read_data;
+                        if (`mem_read_valid) begin
+                            acc = `mem_read_data;
                         end else begin
                             state = MEMORY;
                         end
@@ -159,6 +179,11 @@ always_ff @(posedge clk) begin
                     end
                 endcase
             end
+
+            HALT: begin
+                $display("Reached halt state.");
+                $finish;
+            end
         endcase
 
         `ifdef DEBUG if (mem_valid) $display("\tmem addr=%x w=%b", mem_address, mem_write); `endif