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| author | Julian Blake Kongslie | 2021-04-05 10:20:02 -0700 |
|---|---|---|
| committer | Julian Blake Kongslie | 2021-04-05 10:20:02 -0700 |
| commit | 6a1c04608090cc8fc88aafac0b4899e4cbb9cae9 (patch) | |
| tree | 9a03984357020c00dfeed299a8b321f832a48bd4 /sim | |
| parent | Make PC ADDR-sized rather than DATA-sized for now (diff) | |
| download | noncpu-6a1c04608090cc8fc88aafac0b4899e4cbb9cae9.tar.xz | |
Change our simulator timing model to use continuous assignment guards.
Instead of depending on verilator getting $past right, this (ab-)uses
the SystemVerilog scheduling model which allows us to get a consistent
view of the universe by "isolating" the blocking updates. Easier to code
to and seems to be more reliable in verilator.
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