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-rw-r--r--Makefile2
-rw-r--r--hdl/top.sv31
-rw-r--r--mem/mem.hex53
3 files changed, 62 insertions, 24 deletions
diff --git a/Makefile b/Makefile
index f4a0da8..24e2692 100644
--- a/Makefile
+++ b/Makefile
@@ -9,7 +9,7 @@ sim: build/Vtop
9 9
10build/Vtop: $(SOURCES) $(COLLATERAL) 10build/Vtop: $(SOURCES) $(COLLATERAL)
11 @mkdir -p build 11 @mkdir -p build
12 verilator +1800-2017ext+sv -Wall -Wno-BLKSEQ -Wno-UNUSED -O3 -Ihdl $(OPTS) --Mdir build --trace --cc --build -j --exe --top-module top $(SOURCES) 12 verilator +1800-2017ext+sv -Wall -Wno-BLKSEQ -Wno-UNUSED -Wno-WIDTH -O3 -Ihdl $(OPTS) --Mdir build --trace --cc --build -j --exe --top-module top $(SOURCES)
13 13
14clean: 14clean:
15 rm -rf build 15 rm -rf build
diff --git a/hdl/top.sv b/hdl/top.sv
index 8524b63..aa5a4e2 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -43,6 +43,7 @@ bit [DATA_BITS-1:0] pc;
43bit [3:0] opcode; 43bit [3:0] opcode;
44bit [7:0] operand; 44bit [7:0] operand;
45bit [DATA_BITS-1:0] acc; 45bit [DATA_BITS-1:0] acc;
46bit [DATA_BITS-1:0] idx;
46 47
47enum 48enum
48 { FETCH 49 { FETCH
@@ -56,6 +57,7 @@ always_ff @(posedge clk) begin
56 tx_data = 0; 57 tx_data = 0;
57 pc = 0; 58 pc = 0;
58 acc = 0; 59 acc = 0;
60 idx = 0;
59 state = state.first; 61 state = state.first;
60 end else begin 62 end else begin
61 if (`tx_ready) tx_valid = 0; 63 if (`tx_ready) tx_valid = 0;
@@ -68,18 +70,31 @@ always_ff @(posedge clk) begin
68 end 70 end
69 71
70 DECODE: begin 72 DECODE: begin
73 //$display("%x %x:%x (acc=%x idx=%x)", pc, opcode, operand, acc, idx);
71 state = FETCH; 74 state = FETCH;
72 case (opcode) 75 case (opcode)
73 'b000: acc = {{4{operand[7]}}, operand}; 76 'h0: acc = {{4{operand[7]}}, operand};
74 'b001: begin 77 'h1: acc = mem[idx + operand];
75 if (tx_valid) begin 78 'h2: mem[idx + operand] = acc;
76 state = DECODE; 79 'h3: if (acc != operand) ++pc;
77 end else begin 80 'h4: pc = pc + {{4{operand[7]}}, operand};
78 tx_valid = 1; 81 'hf: begin
79 tx_data = acc[7:0]; 82 if (operand[0]) ++acc;
83 if (operand[1]) --acc;
84 if (operand[2]) ++idx;
85 if (operand[3]) --idx;
86 if (operand[4]) {idx, acc} = {acc, idx};
87 if (operand[5]) idx = acc;
88 if (operand[6]) begin
89 if (tx_valid) begin
90 state = DECODE;
91 end else begin
92 tx_valid = 1;
93 tx_data = acc[7:0];
94 end
80 end 95 end
96 if (operand[7]) state = DECODE;
81 end 97 end
82 'b111: state = DECODE;
83 endcase 98 endcase
84 end 99 end
85 endcase 100 endcase
diff --git a/mem/mem.hex b/mem/mem.hex
index 6d096bb..7923fb7 100644
--- a/mem/mem.hex
+++ b/mem/mem.hex
@@ -1,18 +1,41 @@
1@0 1@0
2 2
3048 100 // H 3040 // %acc = 0x40
4065 100 // e 4f20 // %idx = %acc
506c 100 // l
606c 100 // l
706f 100 // o
802c 100 // ,
9020 100 // ' '
10077 100 // w
1106f 100 // o
12072 100 // r
1306c 100 // l
14064 100 // d
15021 100 // !
1600a 100 // \n
17 5
18700 6// loop: (addr 2)
7100 // %acc = [%idx]
8300 402 // if (%acc == 0) { %pc = exit }
9f44 // ++%idx; tx %acc
104fb // jmp loop
11// exit: (addr 7)
12
13f80 // hcf
14
15@40
16
17048 // H
18065 // e
1906c // l
2006c // l
2106f // o
2202c // ,
23020 // ' '
24077 // w
2506f // o
26072 // r
2706c // l
28064 // d
29021 // !
3000a // \n
31
32000
33
3404f // O
3506f // o
36070 // p
37073 // s
38021 // !
3900a // \n
40
41000