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-rw-r--r--hdl/core.sv8
1 files changed, 4 insertions, 4 deletions
diff --git a/hdl/core.sv b/hdl/core.sv
index 83f4f01..5bee974 100644
--- a/hdl/core.sv
+++ b/hdl/core.sv
@@ -59,7 +59,7 @@ jtag_uart
59 , .tx_data(tx_data) 59 , .tx_data(tx_data)
60 ); 60 );
61 61
62bit [ADDR_BITS-1:ADDR_BITS-6] page; 62bit [ADDR_BITS-1:7] page;
63 63
64bit [ADDR_BITS-1:0] pc; 64bit [ADDR_BITS-1:0] pc;
65bit [2:0] opcode; 65bit [2:0] opcode;
@@ -80,7 +80,7 @@ enum
80 , PREINC 80 , PREINC
81 , AGEN 81 , AGEN
82 , EXEC 82 , EXEC
83 , STORE 83 , MEMWAIT
84 , HALT 84 , HALT
85 } state; 85 } state;
86 86
@@ -104,7 +104,7 @@ always_ff @(posedge clk) begin
104 mem_write = 0; 104 mem_write = 0;
105 if (`lag(mem_ready)) begin 105 if (`lag(mem_ready)) begin
106 state = DECODE; 106 state = DECODE;
107 page = pc[ADDR_BITS-1:ADDR_BITS-6]; 107 page = pc[ADDR_BITS-1:7];
108 ++pc; 108 ++pc;
109 end 109 end
110 end 110 end
@@ -169,7 +169,7 @@ always_ff @(posedge clk) begin
169 mem_valid = 1; 169 mem_valid = 1;
170 mem_write = 1; 170 mem_write = 1;
171 mem_write_data = address[DATA_BITS-1:0]; 171 mem_write_data = address[DATA_BITS-1:0];
172 case (opcode) begin 172 case (opcode)
173 'b000, 'b001, 'b010: state = `lag(mem_ready) ? PREINC : AGEN; 173 'b000, 'b001, 'b010: state = `lag(mem_ready) ? PREINC : AGEN;
174 'b011, 'b100, 'b101: state = `lag(mem_ready) ? PREINC : EXEC; 174 'b011, 'b100, 'b101: state = `lag(mem_ready) ? PREINC : EXEC;
175 endcase 175 endcase