diff options
| -rw-r--r-- | hdl/top.sv | 6 |
1 files changed, 3 insertions, 3 deletions
| @@ -64,7 +64,7 @@ jtag_uart | |||
| 64 | , .tx_data(tx_data) | 64 | , .tx_data(tx_data) |
| 65 | ); | 65 | ); |
| 66 | 66 | ||
| 67 | bit [DATA_BITS-1:0] pc; | 67 | bit [ADDR_BITS-1:0] pc; |
| 68 | bit [3:0] opcode; | 68 | bit [3:0] opcode; |
| 69 | bit [7:0] operand; | 69 | bit [7:0] operand; |
| 70 | bit [DATA_BITS-1:0] acc; | 70 | bit [DATA_BITS-1:0] acc; |
| @@ -97,7 +97,7 @@ always_ff @(posedge clk) begin | |||
| 97 | case (state) | 97 | case (state) |
| 98 | FETCH: begin | 98 | FETCH: begin |
| 99 | mem_valid = 1; | 99 | mem_valid = 1; |
| 100 | mem_address = {2'b0, pc}; | 100 | mem_address_ = pc; |
| 101 | mem_write = 0; | 101 | mem_write = 0; |
| 102 | if (`mem_ready) begin | 102 | if (`mem_ready) begin |
| 103 | state = DECODE; | 103 | state = DECODE; |
| @@ -157,7 +157,7 @@ always_ff @(posedge clk) begin | |||
| 157 | mem_write = 0; | 157 | mem_write = 0; |
| 158 | end | 158 | end |
| 159 | if (`mem_read_valid) begin | 159 | if (`mem_read_valid) begin |
| 160 | address = `mem_read_data; | 160 | address = {{(ADDR_BITS - DATA_BITS){1'b0}}, `mem_read_data}; |
| 161 | state = AGEN; | 161 | state = AGEN; |
| 162 | end | 162 | end |
| 163 | end | 163 | end |
