diff options
| -rw-r--r-- | altera/clocks.sdc | 2 | ||||
| -rw-r--r-- | tcl/init.tcl | 2 |
2 files changed, 2 insertions, 2 deletions
diff --git a/altera/clocks.sdc b/altera/clocks.sdc index 239c91a..15d4482 100644 --- a/altera/clocks.sdc +++ b/altera/clocks.sdc | |||
| @@ -1,3 +1,3 @@ | |||
| 1 | # This is the clock for timing analysis, not timing-driven synthesis. | 1 | # This is the clock for timing analysis, not timing-driven synthesis. |
| 2 | # See init.tcl for the other clock. | 2 | # See init.tcl for the other clock. |
| 3 | create_clock -period "50 MHz" clk | 3 | create_clock -period "45 MHz" clk |
diff --git a/tcl/init.tcl b/tcl/init.tcl index 039af91..96ed9de 100644 --- a/tcl/init.tcl +++ b/tcl/init.tcl | |||
| @@ -16,7 +16,7 @@ pin J15 reset_n | |||
| 16 | 16 | ||
| 17 | # This is the clock for timing-driven synthesis, not timing analysis. | 17 | # This is the clock for timing-driven synthesis, not timing analysis. |
| 18 | # See clocks.sdf for the other clock. | 18 | # See clocks.sdf for the other clock. |
| 19 | create_base_clock -fmax "50 MHz" clk | 19 | create_base_clock -fmax "45 MHz" clk |
| 20 | 20 | ||
| 21 | proc add_files {typ ext dir} { | 21 | proc add_files {typ ext dir} { |
| 22 | foreach name [glob -nocomplain -directory $dir -type f "*.$ext"] { | 22 | foreach name [glob -nocomplain -directory $dir -type f "*.$ext"] { |