2 files changed, 15 insertions, 0 deletions

diff --git a/altera/clocks.sdc b/altera/clocks.sdc
new file mode 100644
index 0000000..239c91a
--- /dev/null
+++ b/altera/clocks.sdc
@@ -0,0 +1,3 @@
+# This is the clock for timing analysis, not timing-driven synthesis.
+# See init.tcl for the other clock.
+create_clock -period "50 MHz" clk
diff --git a/altera/jtag.cdf b/altera/jtag.cdf
new file mode 100644
index 0000000..ac80090
--- /dev/null
+++ b/altera/jtag.cdf
@@ -0,0 +1,12 @@
+JedecChain;
+    FileRevision(JESD32A);
+    DefaultMfr(6E);
+
+    P ActionCode(Ign)
+        Device PartName(10CL025Y) MfrSpec(OpMask(0));
+
+ChainEnd;
+
+AlteraBegin;
+    ChainType(JTAG);
+AlteraEnd;