1 files changed, 76 insertions, 11 deletions

diff --git a/hdl/core.sv b/hdl/core.sv
index 14660f5..b607e4b 100644
--- a/hdl/core.sv
+++ b/hdl/core.sv
@@ -50,12 +50,18 @@ module core
     );
 
 bit run;
+bit int_enable;
+bit int_delay;
+bit int_request;
+
 bit switch_start_observed;
 bit switch_load_add_observed;
 bit switch_dep_observed;
 bit switch_exam_observed;
 bit switch_cont_observed;
+
 assign led_run = run;
+assign led_ion = int_enable;
 
 bit mem_ready;
 bit mem_valid;
@@ -134,14 +140,19 @@ assign led_jmp = opcode == 5;
 assign led_iot = opcode == 6;
 assign led_opr = opcode == 7;
 
-bit kbd_valid;
-bit [DATA_BITS-1:0] kbd_data;
+bit tti_int_enable;
+bit tti_valid;
+bit [DATA_BITS-1:0] tti_data;
 
 bit i;
 bit z;
 bit [6:0] wip;
 bit [ADDR_BITS-1:0] address;
 
+assign int_request =
+    (tti_int_enable && tti_valid)
+    ;
+
 enum
     {   FETCH
     ,   DECODE
@@ -162,6 +173,8 @@ assign led_pause = state == MEMWAIT || state == HALT;
 always_ff @(posedge clk) begin
     if (reset) begin
         run = 0;
+        int_enable = 0;
+        int_delay = 0;
         switch_start_observed = 0;
         switch_load_add_observed = 0;
         switch_dep_observed = 0;
@@ -175,12 +188,15 @@ always_ff @(posedge clk) begin
         led_pc = pc;
         acc = 0;
         link = 1;
-        kbd_valid = 0;
+        tti_int_enable = 0;
+        tti_valid = 0;
         state = state.first;
     end else begin
         if (switch_start && !switch_start_observed) begin
             switch_start_observed = 1;
             run = 1;
+            int_enable = 0;
+            int_delay = 0;
             mem_valid = 0;
             acc = 0;
             link = 1;
@@ -226,8 +242,8 @@ always_ff @(posedge clk) begin
 
         if (`lag(tx_ready)) tx_valid = 0;
         if (rx_ready && `lag(rx_valid)) begin
-            kbd_valid = 1;
-            kbd_data = {4'b0, 1'b1, `lag(rx_data[6:0])};
+            tti_valid = 1;
+            tti_data = {4'b0, 1'b1, `lag(rx_data[6:0])};
         end
 
         if (run) begin
@@ -245,12 +261,25 @@ always_ff @(posedge clk) begin
                 end
 
                 DECODE: begin
+                    automatic bit go;
+                    go = 0;
                     mem_valid = 0;
                     mem_write = 0;
-                    if (`lag(mem_read_valid)) begin
+                    if (int_enable && int_request) begin
+                        int_enable = 0;
+                        int_delay = 0;
+                        --pc;
+                        opcode = 'b100;
+                        operand = 'b000000;
+                        go = 1;
+                    end else if (`lag(mem_read_valid)) begin
                         state = FETCH;
                         led_memdata = `lag(mem_read_data);
                         {opcode, operand} = `lag(mem_read_data);
+                        go = 1;
+                    end
+                    if (go) begin
+                        int_enable = int_delay;
     //                    $display("%o: decode %o %o", pc-1, opcode, operand);
                         // verilator lint_off WIDTH
     //                    $display("%o  %b %o  0000", 14'(pc-1), link, acc);
@@ -332,16 +361,51 @@ always_ff @(posedge clk) begin
                                 case (operand[8:3])
                                     'o00: begin
                                         case (operand[2:0])
-                                            'o0, 'o1: ;
+                                            'o0: begin
+                                                if (int_enable)
+                                                    ++pc;
+                                                int_enable = 0;
+                                                int_delay = 0;
+                                            end
+                                            'o1: int_delay = 1;
+                                            'o2: begin
+                                                int_enable = 0;
+                                                int_delay = 0;
+                                            end
+                                            'o3: begin
+                                                if (int_request)
+                                                    ++pc;
+                                            end
+                                            'o4: acc = {link, 1'b0/*gt*/, int_request, 1'b0/*ii*/, int_enable, 1'b0/*u*/, 3'b0/*if*/, 3'b0/*df*/};
+                                            'o5: begin
+                                                link = acc[11];
+                                                if (acc[7]) begin
+                                                    int_delay = 1;
+                                                end else begin
+                                                    int_enable = 0;
+                                                    int_delay = 0;
+                                                end
+                                            end
+                                            'o7: begin
+                                                int_enable = 0;
+                                                int_delay = 0;
+                                                acc = 0;
+                                                link = 1;
+                                                tx_valid = 0;
+                                                tti_valid = 0;
+                                            end
                                             default: $display("%o: unsupported 600%o op", pc-1, operand[2:0]);
                                         endcase
                                     end
                                     'o03: begin
                                         case (operand[2:0])
-                                            'o1: if (kbd_valid) pc++;
+                                            'o1: if (tti_valid) pc++;
+                                            'o5: begin
+                                                tti_int_enable = acc[0];
+                                            end
                                             'o6: begin
-                                                acc = kbd_data;
-                                                kbd_valid = 0;
+                                                acc = tti_data;
+                                                tti_valid = 0;
                                             end
                                             default: begin
                                                 $display("%o: unsupported keyboard op %o", pc-1, operand[2:0]);
@@ -479,6 +543,7 @@ always_ff @(posedge clk) begin
                 MEMWAIT: state = `lag(mem_ready) ? FETCH : MEMWAIT;
 
                 HALT: begin
+                    run = 0;
                     $display("\nhalt state reached");
                     $finish;
                 end
@@ -490,7 +555,7 @@ always_ff @(posedge clk) begin
             if (state == FETCH && switch_sing_inst)
                 run = 0;
 
-            rx_ready = !kbd_valid;
+            rx_ready = !tti_valid;
         end
     end
 end