diff options
Diffstat (limited to 'hdl/top.sv')
| -rw-r--r-- | hdl/top.sv | 89 |
1 files changed, 89 insertions, 0 deletions
diff --git a/hdl/top.sv b/hdl/top.sv new file mode 100644 index 0000000..8524b63 --- /dev/null +++ b/hdl/top.sv | |||
| @@ -0,0 +1,89 @@ | |||
| 1 | `include "util.svh" | ||
| 2 | |||
| 3 | module top | ||
| 4 | #( ADDR_BITS = 14 | ||
| 5 | , DATA_BITS = 12 | ||
| 6 | ) | ||
| 7 | ( input bit clk // verilator public | ||
| 8 | , input bit reset_n // verilator public | ||
| 9 | ); | ||
| 10 | |||
| 11 | bit reset = 0; | ||
| 12 | bit have_reset = 0; | ||
| 13 | always_ff @(posedge clk) if (reset) have_reset <= 1; | ||
| 14 | assign reset = !reset_n || !have_reset; | ||
| 15 | |||
| 16 | bit [DATA_BITS-1:0] mem [0:(1<<ADDR_BITS)-1]; | ||
| 17 | initial $readmemh("mem/mem.hex", mem); | ||
| 18 | |||
| 19 | bit rx_ready; | ||
| 20 | bit rx_valid; | ||
| 21 | bit [7:0] rx_data; | ||
| 22 | |||
| 23 | bit tx_ready; | ||
| 24 | bit tx_valid; | ||
| 25 | bit [7:0] tx_data; | ||
| 26 | |||
| 27 | jtag_uart | ||
| 28 | #( .INSTANCE(0) | ||
| 29 | ) uart0 | ||
| 30 | ( .clk(clk) | ||
| 31 | , .reset(reset) | ||
| 32 | |||
| 33 | , .rx_ready(rx_ready) | ||
| 34 | , .rx_valid(rx_valid) `define rx_valid `past(rx_valid) | ||
| 35 | , .rx_data(rx_data) `define rx_data `past(rx_data) | ||
| 36 | |||
| 37 | , .tx_ready(tx_ready) `define tx_ready `past(tx_ready) | ||
| 38 | , .tx_valid(tx_valid) | ||
| 39 | , .tx_data(tx_data) | ||
| 40 | ); | ||
| 41 | |||
| 42 | bit [DATA_BITS-1:0] pc; | ||
| 43 | bit [3:0] opcode; | ||
| 44 | bit [7:0] operand; | ||
| 45 | bit [DATA_BITS-1:0] acc; | ||
| 46 | |||
| 47 | enum | ||
| 48 | { FETCH | ||
| 49 | , DECODE | ||
| 50 | } state; | ||
| 51 | |||
| 52 | always_ff @(posedge clk) begin | ||
| 53 | if (reset) begin | ||
| 54 | rx_ready = 0; | ||
| 55 | tx_valid = 0; | ||
| 56 | tx_data = 0; | ||
| 57 | pc = 0; | ||
| 58 | acc = 0; | ||
| 59 | state = state.first; | ||
| 60 | end else begin | ||
| 61 | if (`tx_ready) tx_valid = 0; | ||
| 62 | |||
| 63 | case (state) | ||
| 64 | FETCH: begin | ||
| 65 | {opcode, operand} = mem[{2'b0, pc}]; | ||
| 66 | ++pc; | ||
| 67 | state = DECODE; | ||
| 68 | end | ||
| 69 | |||
| 70 | DECODE: begin | ||
| 71 | state = FETCH; | ||
| 72 | case (opcode) | ||
| 73 | 'b000: acc = {{4{operand[7]}}, operand}; | ||
| 74 | 'b001: begin | ||
| 75 | if (tx_valid) begin | ||
| 76 | state = DECODE; | ||
| 77 | end else begin | ||
| 78 | tx_valid = 1; | ||
| 79 | tx_data = acc[7:0]; | ||
| 80 | end | ||
| 81 | end | ||
| 82 | 'b111: state = DECODE; | ||
| 83 | endcase | ||
| 84 | end | ||
| 85 | endcase | ||
| 86 | end | ||
| 87 | end | ||
| 88 | |||
| 89 | endmodule | ||
