1 files changed, 34 insertions, 31 deletions

diff --git a/hdl/top.sv b/hdl/top.sv
index 00d0cab..71a5a48 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -68,7 +68,6 @@ bit [DATA_BITS-1:0] pc;
 bit [3:0] opcode;
 bit [7:0] operand;
 bit [DATA_BITS-1:0] acc;
-bit [DATA_BITS-1:0] idx;
 
 bit [ADDR_BITS-1:0] address;
 bit [DATA_BITS-1:0] sign_extended_operand;
@@ -91,10 +90,9 @@ always_ff @(posedge clk) begin
         tx_data = 0;
         pc = 0;
         acc = 0;
-        idx = 0;
         state = state.first;
     end else begin
-        `ifdef DEBUG $display("s=%0d pc=%x (acc=%x idx=%x) (mem %b:%x)", state, pc, acc, idx, `mem_read_valid, `mem_read_data); `endif
+        `ifdef DEBUG $display("s=%0d pc=%x (acc=%x) (mem %b:%x)", state, pc, acc, `mem_read_valid, `mem_read_data); `endif
         if (`tx_ready) tx_valid = 0;
 
         case (state)
@@ -118,29 +116,33 @@ always_ff @(posedge clk) begin
                     sign_extended_operand = {{(DATA_BITS-8){operand[7]}}, operand};
                     `ifdef DEBUG $display("\tdecode %x:%x", opcode, operand); `endif
                     case (opcode)
-                        'h0: acc = sign_extended_operand;
-                        'h1, 'h2: begin
+                        'h0: begin
+                            if (operand[0]) acc = 0;
+                            if (operand[1]) ++acc;
+                            if (operand[2]) --acc;
+                            if (operand[6]) state = MEMORY;
+                            if (operand[7]) state = HALT;
+                        end
+                        'h1: acc = sign_extended_operand;
+                        'h2, 'h3: begin
                             address = {7'b0, operand[6:0]};
                             state = operand[7] ? INDIRECT : AGEN;
                         end
-                        'h3: if (acc != sign_extended_operand) ++pc;
-                        'h4: pc = pc + sign_extended_operand;
+                        'h4: if (acc != sign_extended_operand) ++pc;
                         'h5: begin
+                            if (operand[7]) begin
+                                address = {7'b0, operand[6:0]};
+                                state = INDIRECT;
+                            end else begin
+                                pc = pc + {{(ADDR_BITS-7){operand[6]}}, operand[6:0]};
+                            end
+                        end
+                        'h6: begin
                             mem_write_data = acc % 10 + 'h30;
                             acc = acc / 10;
                             address = {7'b0, operand[6:0]};
                             state = operand[7] ? INDIRECT : AGEN;
                         end
-                        'hf: begin
-                            if (operand[0]) ++acc;
-                            if (operand[1]) --acc;
-                            if (operand[2]) ++idx;
-                            if (operand[3]) --idx;
-                            if (operand[4]) {idx, acc} = {acc, idx};
-                            if (operand[5]) idx = acc;
-                            if (operand[6]) state = MEMORY;
-                            if (operand[7]) state = HALT;
-                        end
                     endcase
                 end
             end
@@ -169,21 +171,22 @@ always_ff @(posedge clk) begin
                 state = FETCH;
                 `ifdef DEBUG $display("\tagen"); `endif
                 case (opcode)
-                    'h1: begin
+                    'h2: begin
                         mem_valid = 1;
-                        mem_address = address + idx;
+                        mem_address = address;
                         state = `mem_ready ? MEMORY : AGEN;
                     end
-                    'h2: begin
+                    'h3: begin
                         mem_valid = 1;
-                        mem_address = address + idx;
+                        mem_address = address;
                         mem_write = 1;
                         mem_write_data = acc;
                         state = `mem_ready ? FETCH : AGEN;
                     end
-                    'h5: begin
+                    'h5: pc = address;
+                    'h6: begin
                         mem_valid = 1;
-                        mem_address = address + idx;
+                        mem_address = address;
                         mem_write = 1;
                         state = `mem_ready ? FETCH : AGEN;
                     end
@@ -198,14 +201,7 @@ always_ff @(posedge clk) begin
                 state = FETCH;
                 `ifdef DEBUG $display("\tstall"); `endif
                 case (opcode)
-                    'h1: begin
-                        if (`mem_read_valid) begin
-                            acc = acc + `mem_read_data;
-                        end else begin
-                            state = MEMORY;
-                        end
-                    end
-                    'hf: begin
+                    'h0: begin
                         if (operand[6]) begin
                             if (tx_valid) begin
                                 state = MEMORY;
@@ -215,6 +211,13 @@ always_ff @(posedge clk) begin
                             end
                         end
                     end
+                    'h2: begin
+                        if (`mem_read_valid) begin
+                            acc = acc + `mem_read_data;
+                        end else begin
+                            state = MEMORY;
+                        end
+                    end
                 endcase
             end