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-rw-r--r--hdl/jtag_uart.sv37
-rw-r--r--hdl/mem.sv26
-rw-r--r--hdl/top.sv105
-rw-r--r--hdl/util.svh7
4 files changed, 74 insertions, 101 deletions
diff --git a/hdl/jtag_uart.sv b/hdl/jtag_uart.sv
index 2b5f334..096b1c9 100644
--- a/hdl/jtag_uart.sv
+++ b/hdl/jtag_uart.sv
@@ -18,13 +18,6 @@ module jtag_uart
18 , input bit [7:0] tx_data 18 , input bit [7:0] tx_data
19 ); 19 );
20 20
21`input(rx_ready)
22`output(rx_valid)
23`output(rx_data)
24`output(tx_ready)
25`input(tx_valid)
26`input(tx_data)
27
28`ifdef SYNTHESIS 21`ifdef SYNTHESIS
29 22
30alt_jtag_atlantic 23alt_jtag_atlantic
@@ -35,12 +28,12 @@ alt_jtag_atlantic
35 ) real_jtag 28 ) real_jtag
36 ( .clk(clk) 29 ( .clk(clk)
37 , .rst_n(!reset) 30 , .rst_n(!reset)
38 , .r_dat(tx_data_) 31 , .r_dat(tx_data)
39 , .r_val(tx_valid_) 32 , .r_val(tx_valid)
40 , .r_ena(tx_ready_) 33 , .r_ena(tx_ready)
41 , .t_dat(rx_data_) 34 , .t_dat(rx_data)
42 , .t_dav(rx_ready_) 35 , .t_dav(rx_ready)
43 , .t_ena(rx_valid_) 36 , .t_ena(rx_valid)
44 ); 37 );
45 38
46`else 39`else
@@ -55,34 +48,34 @@ bit [7:0] tx_b_data;
55 48
56always_ff @(posedge clk) begin 49always_ff @(posedge clk) begin
57 if (reset) begin 50 if (reset) begin
58 rx_valid_ = 0; 51 rx_valid = 0;
59 tx_ready_ = 0; 52 tx_ready = 0;
60 sim_rx_addr = 0; 53 sim_rx_addr = 0;
61 tx_b_valid = 0; 54 tx_b_valid = 0;
62 end else begin 55 end else begin
63 automatic bit [7:0] sim_rx_data = sim_rx_rom[sim_rx_addr]; 56 automatic bit [7:0] sim_rx_data = sim_rx_rom[sim_rx_addr];
64 57
65 // RX logic 58 // RX logic
66 if (rx_ready_) rx_valid_ = 0; 59 if (`lag(rx_ready)) rx_valid = 0;
67 if (!rx_valid_ && (sim_rx_data != 0)) begin 60 if (!rx_valid && (sim_rx_data != 0)) begin
68`ifdef JTAG_UART_LOCAL_ECHO 61`ifdef JTAG_UART_LOCAL_ECHO
69 $write("%s", sim_rx_data); 62 $write("%s", sim_rx_data);
70`endif 63`endif
71 rx_valid_ = 1; 64 rx_valid = 1;
72 rx_data_ = sim_rx_data; 65 rx_data = sim_rx_data;
73 ++sim_rx_addr; 66 ++sim_rx_addr;
74 end 67 end
75 68
76 // TX logic 69 // TX logic
77 if (tx_ready_ && tx_valid_) begin 70 if (tx_ready && `lag(tx_valid)) begin
78 tx_b_valid = 1; 71 tx_b_valid = 1;
79 tx_b_data = tx_data_; 72 tx_b_data = `lag(tx_data);
80 end 73 end
81 if (tx_b_valid) begin 74 if (tx_b_valid) begin
82 $write("%s", tx_b_data); 75 $write("%s", tx_b_data);
83 tx_b_valid = 0; 76 tx_b_valid = 0;
84 end 77 end
85 tx_ready_ = !tx_b_valid; 78 tx_ready = !tx_b_valid;
86 end 79 end
87end 80end
88 81
diff --git a/hdl/mem.sv b/hdl/mem.sv
index c362e37..9c5f567 100644
--- a/hdl/mem.sv
+++ b/hdl/mem.sv
@@ -18,32 +18,24 @@ parameter ADDR_BITS;
18parameter DATA_BITS; 18parameter DATA_BITS;
19parameter INIT_FILE; 19parameter INIT_FILE;
20 20
21`output(ready)
22`input(valid)
23`input(write)
24`input(address)
25`input(write_data)
26`output(read_valid)
27`output(read_data)
28
29bit [DATA_BITS-1:0] storage [0:(1<<ADDR_BITS)-1]; 21bit [DATA_BITS-1:0] storage [0:(1<<ADDR_BITS)-1];
30initial $readmemh(INIT_FILE, storage); 22initial $readmemh(INIT_FILE, storage);
31 23
32always_ff @(posedge clk) begin 24always_ff @(posedge clk) begin
33 if (reset) begin 25 if (reset) begin
34 ready_ = 0; 26 ready = 0;
35 read_valid_ = 0; 27 read_valid = 0;
36 end else begin 28 end else begin
37 read_valid_ = 0; 29 read_valid = 0;
38 if (ready_ && valid_) begin 30 if (ready && `lag(valid)) begin
39 if (write_) begin 31 if (`lag(write)) begin
40 storage[address_] = write_data_; 32 storage[`lag(address)] = `lag(write_data);
41 end else begin 33 end else begin
42 read_valid_ = 1; 34 read_valid = 1;
43 read_data_ = storage[address_]; 35 read_data = storage[`lag(address)];
44 end 36 end
45 end 37 end
46 ready_ = 1; 38 ready = 1;
47 end 39 end
48end 40end
49 41
diff --git a/hdl/top.sv b/hdl/top.sv
index a1cdbf7..3cda157 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -41,14 +41,6 @@ mem
41 , .read_data(mem_read_data) 41 , .read_data(mem_read_data)
42 ); 42 );
43 43
44`input(mem_ready)
45`output(mem_valid)
46`output(mem_address)
47`output(mem_write)
48`output(mem_write_data)
49`input(mem_read_valid)
50`input(mem_read_data)
51
52bit rx_ready; 44bit rx_ready;
53bit rx_valid; 45bit rx_valid;
54bit [7:0] rx_data; 46bit [7:0] rx_data;
@@ -72,13 +64,6 @@ jtag_uart
72 , .tx_data(tx_data) 64 , .tx_data(tx_data)
73 ); 65 );
74 66
75`output(rx_ready)
76`input(rx_valid)
77`input(rx_data)
78`input(tx_ready)
79`output(tx_valid)
80`output(tx_data)
81
82bit [ADDR_BITS-1:0] pc; 67bit [ADDR_BITS-1:0] pc;
83bit [3:0] opcode; 68bit [3:0] opcode;
84bit [7:0] operand; 69bit [7:0] operand;
@@ -99,33 +84,33 @@ enum
99 84
100always_ff @(posedge clk) begin 85always_ff @(posedge clk) begin
101 if (reset) begin 86 if (reset) begin
102 mem_valid_ = 0; 87 mem_valid = 0;
103 rx_ready_ = 0; 88 rx_ready = 0;
104 tx_valid_ = 0; 89 tx_valid = 0;
105 tx_data_ = 0; 90 tx_data = 0;
106 pc = 0; 91 pc = 0;
107 acc = 0; 92 acc = 0;
108 state = state.first; 93 state = state.first;
109 end else begin 94 end else begin
110 if (tx_ready_) tx_valid_ = 0; 95 if (`lag(tx_ready)) tx_valid = 0;
111 96
112 case (state) 97 case (state)
113 FETCH: begin 98 FETCH: begin
114 mem_valid_ = 1; 99 mem_valid = 1;
115 mem_address_ = pc; 100 mem_address = pc;
116 mem_write_ = 0; 101 mem_write = 0;
117 if (mem_ready_) begin 102 if (`lag(mem_ready)) begin
118 state = DECODE; 103 state = DECODE;
119 ++pc; 104 ++pc;
120 end 105 end
121 end 106 end
122 107
123 DECODE: begin 108 DECODE: begin
124 mem_valid_ = 0; 109 mem_valid = 0;
125 mem_write_ = 0; 110 mem_write = 0;
126 if (mem_read_valid_) begin 111 if (`lag(mem_read_valid)) begin
127 state = FETCH; 112 state = FETCH;
128 {opcode, operand} = mem_read_data_; 113 {opcode, operand} = `lag(mem_read_data);
129 sign_extended_operand = {{(DATA_BITS-8){operand[7]}}, operand}; 114 sign_extended_operand = {{(DATA_BITS-8){operand[7]}}, operand};
130 case (opcode) 115 case (opcode)
131 'h0: begin 116 'h0: begin
@@ -150,7 +135,7 @@ always_ff @(posedge clk) begin
150 end 135 end
151 end 136 end
152 'h6: begin 137 'h6: begin
153 mem_write_data_ = acc % 10 + 'h30; 138 mem_write_data = acc % 10 + 'h30;
154 acc = acc / 10; 139 acc = acc / 10;
155 address = {7'b0, operand[6:0]}; 140 address = {7'b0, operand[6:0]};
156 state = operand[7] ? INDIRECT : AGEN; 141 state = operand[7] ? INDIRECT : AGEN;
@@ -160,70 +145,70 @@ always_ff @(posedge clk) begin
160 end 145 end
161 146
162 INDIRECT: begin 147 INDIRECT: begin
163 mem_valid_ = 1; 148 mem_valid = 1;
164 mem_write_ = 0; 149 mem_write = 0;
165 mem_address_ = address; 150 mem_address = address;
166 state = mem_ready_ ? INDIRECTED : INDIRECT; 151 state = `lag(mem_ready) ? INDIRECTED : INDIRECT;
167 end 152 end
168 153
169 INDIRECTED: begin 154 INDIRECTED: begin
170 if (mem_ready_) begin 155 if (`lag(mem_ready)) begin
171 mem_valid_ = 0; 156 mem_valid = 0;
172 mem_write_ = 0; 157 mem_write = 0;
173 end 158 end
174 if (mem_read_valid_) begin 159 if (`lag(mem_read_valid)) begin
175 address = {{(ADDR_BITS - DATA_BITS){1'b0}}, mem_read_data_}; 160 address = {{(ADDR_BITS - DATA_BITS){1'b0}}, `lag(mem_read_data)};
176 state = AGEN; 161 state = AGEN;
177 end 162 end
178 end 163 end
179 164
180 AGEN: begin 165 AGEN: begin
181 mem_valid_ = 0; 166 mem_valid = 0;
182 mem_write_ = 0; 167 mem_write = 0;
183 state = FETCH; 168 state = FETCH;
184 case (opcode) 169 case (opcode)
185 'h2: begin 170 'h2: begin
186 mem_valid_ = 1; 171 mem_valid = 1;
187 mem_address_ = address; 172 mem_address = address;
188 state = mem_ready_ ? MEMORY : AGEN; 173 state = `lag(mem_ready) ? MEMORY : AGEN;
189 end 174 end
190 'h3: begin 175 'h3: begin
191 mem_valid_ = 1; 176 mem_valid = 1;
192 mem_address_ = address; 177 mem_address = address;
193 mem_write_ = 1; 178 mem_write = 1;
194 mem_write_data_ = acc; 179 mem_write_data = acc;
195 state = mem_ready_ ? FETCH : AGEN; 180 state = `lag(mem_ready) ? FETCH : AGEN;
196 end 181 end
197 'h5: pc = address; 182 'h5: pc = address;
198 'h6: begin 183 'h6: begin
199 mem_valid_ = 1; 184 mem_valid = 1;
200 mem_address_ = address; 185 mem_address = address;
201 mem_write_ = 1; 186 mem_write = 1;
202 state = mem_ready_ ? FETCH : AGEN; 187 state = `lag(mem_ready) ? FETCH : AGEN;
203 end 188 end
204 endcase 189 endcase
205 end 190 end
206 191
207 MEMORY: begin 192 MEMORY: begin
208 if (mem_ready_) begin 193 if (`lag(mem_ready)) begin
209 mem_valid_ = 0; 194 mem_valid = 0;
210 mem_write_ = 0; 195 mem_write = 0;
211 end 196 end
212 state = FETCH; 197 state = FETCH;
213 case (opcode) 198 case (opcode)
214 'h0: begin 199 'h0: begin
215 if (operand[6]) begin 200 if (operand[6]) begin
216 if (tx_valid_) begin 201 if (tx_valid) begin
217 state = MEMORY; 202 state = MEMORY;
218 end else begin 203 end else begin
219 tx_valid_ = 1; 204 tx_valid = 1;
220 tx_data_ = acc[7:0]; 205 tx_data = acc[7:0];
221 end 206 end
222 end 207 end
223 end 208 end
224 'h2: begin 209 'h2: begin
225 if (mem_read_valid_) begin 210 if (`lag(mem_read_valid)) begin
226 acc = acc + mem_read_data_; 211 acc = acc + `lag(mem_read_data);
227 end else begin 212 end else begin
228 state = MEMORY; 213 state = MEMORY;
229 end 214 end
diff --git a/hdl/util.svh b/hdl/util.svh
index fa6ddc5..012e2ed 100644
--- a/hdl/util.svh
+++ b/hdl/util.svh
@@ -1,2 +1,5 @@
1`define input(x) type(x) x``_; assign x``_ = x; 1`ifdef SYNTHESIS
2`define output(x) type(x) x``_; assign x = x``_; 2`define lag(x) x
3`else
4`define lag(x) $past(x)
5`endif
generated by cgit v1.2.3 (git 2.51.0) at 2026-04-19 00:33:33 -0700