3 files changed, 9 insertions, 13 deletions

diff --git a/hdl/jtag_uart.sv b/hdl/jtag_uart.sv
index c297811..ad4665e 100644
--- a/hdl/jtag_uart.sv
+++ b/hdl/jtag_uart.sv
@@ -75,11 +75,7 @@ always_ff @(posedge clk) begin
             $write("%s", tx_b_data);
             tx_b_valid = 0;
         end
-`ifdef JTAG_UART_FAST
         tx_ready = !tx_b_valid;
-`else
-        tx_ready = !tx_b_valid && !tx_ready && `tx_valid;
-`endif
     end
 end
 
diff --git a/hdl/top.sv b/hdl/top.sv
index 8c693b3..d224561 100644
--- a/hdl/top.sv
+++ b/hdl/top.sv
@@ -100,7 +100,7 @@ always_ff @(posedge clk) begin
                 mem_valid = 1;
                 mem_address = {2'b0, pc};
                 mem_write = 0;
-                if (mem_ready) begin
+                if (`mem_ready) begin
                     state = DECODE;
                     ++pc;
                 end
@@ -109,9 +109,9 @@ always_ff @(posedge clk) begin
             DECODE: begin
                 mem_valid = 0;
                 mem_write = 0;
-                if (mem_read_valid) begin
+                if (`mem_read_valid) begin
                     state = FETCH;
-                    {opcode, operand} = mem_read_data;
+                    {opcode, operand} = `mem_read_data;
                     sign_extended_operand = {{(DATA_BITS-8){operand[7]}}, operand};
                     `ifdef DEBUG $display("\tdecode %x:%x", opcode, operand); `endif
                     case (opcode)
@@ -143,20 +143,20 @@ always_ff @(posedge clk) begin
                     'h1: begin
                         mem_valid = 1;
                         mem_address = {2'b0, idx + sign_extended_operand};
-                        state = mem_ready ? MEMORY : AGEN;
+                        state = `mem_ready ? MEMORY : AGEN;
                     end
                     'h2: begin
                         mem_valid = 1;
                         mem_address = {2'b0, idx + sign_extended_operand};
                         mem_write = 1;
                         mem_write_data = acc;
-                        state = mem_ready ? FETCH : AGEN;
+                        state = `mem_ready ? FETCH : AGEN;
                     end
                 endcase
             end
 
             MEMORY: begin
-                if (mem_ready) begin
+                if (`mem_ready) begin
                     mem_valid = 0;
                     mem_write = 0;
                 end
@@ -164,8 +164,8 @@ always_ff @(posedge clk) begin
                 `ifdef DEBUG $display("\tstall"); `endif
                 case (opcode)
                     'h1: begin
-                        if (mem_read_valid) begin
-                            acc = mem_read_data;
+                        if (`mem_read_valid) begin
+                            acc = `mem_read_data;
                         end else begin
                             state = MEMORY;
                         end
diff --git a/hdl/util.svh b/hdl/util.svh
index ddba543..db5e4e6 100644
--- a/hdl/util.svh
+++ b/hdl/util.svh
@@ -1,5 +1,5 @@
 `ifdef SYNTHESIS
 `define past(x) x
 `else
-`define past(x) $past(x)
+`define past(x) $sampled(x)
 `endif