summaryrefslogtreecommitdiff
Commit message (Collapse)AuthorAgeFilesLines
* Assembler errors for too-far jumps.Julian Blake Kongslie2021-04-051-0/+2
|
* Change our simulator timing model to use continuous assignment guards.Julian Blake Kongslie2021-04-054-86/+113
| | | | | | | Instead of depending on verilator getting $past right, this (ab-)uses the SystemVerilog scheduling model which allows us to get a consistent view of the universe by "isolating" the blocking updates. Easier to code to and seems to be more reliable in verilator.
* Make PC ADDR-sized rather than DATA-sized for nowJulian Blake Kongslie2021-04-051-3/+3
|
* Remove some old debug messages.Julian Blake Kongslie2021-04-051-11/+1
|
* Longer runtime for verilator before giving up.Julian Blake Kongslie2021-04-051-1/+1
|
* Change build system so verilator doesn't require constant "make clean"s.Julian Blake Kongslie2021-04-052-3/+7
|
* Remove idx, add indirect jumps, renumber opcodes so NOP=0, add absolute ↵Julian Blake Kongslie2021-04-043-117/+133
| | | | labels to asm.rb
* Add indirect memory operations.Julian Blake Kongslie2021-04-043-8/+34
|
* Very fancy improved Fibonacci machine, with HDL convert-to-ASCII functionalityJulian Blake Kongslie2021-04-043-13/+80
|
* Remove unneeded .exe suffixes in bat scripts.Julian Blake Kongslie2021-04-042-4/+4
|
* Change assembler input to make it idempotent.Julian Blake Kongslie2021-04-041-0/+1
|
* Streamlined the Fibonacci program somewhat.Julian Blake Kongslie2021-03-301-17/+10
|
* Add a Fibonacci sequence to the end of output (no ASCII conversion yet)Julian Blake Kongslie2021-03-292-13/+20
|
* Trivial assembler.Julian Blake Kongslie2021-03-292-10/+71
|
* Trivial cleanup of initial memory image.Julian Blake Kongslie2021-03-291-2/+1
|
* Convert to using $sampled instead of $past, for more uniformity.Julian Blake Kongslie2021-03-293-13/+9
|
* Fix WIDTH warnings from verilator.Julian Blake Kongslie2021-03-292-6/+9
|
* Vastly improve the edit-rebuild-debug cycle.Julian Blake Kongslie2021-03-281-0/+7
|
* Possibly slightly less lame.Julian Blake Kongslie2021-03-281-10/+10
|
* Yet another lame attempt.Julian Blake Kongslie2021-03-282-34/+71
|
* Pessimize JTAG UART somewhat.Julian Blake Kongslie2021-03-282-8/+5
|
* Use a separate memory module.Julian Blake Kongslie2021-03-282-9/+110
| | | | Hopefully this will infer a memory the way we want in Quartus.
* Some more interesting opcodes.Julian Blake Kongslie2021-03-283-24/+62
|
* Initial commit.Julian Blake Kongslie2021-03-2816-0/+356