| Commit message (Collapse) | Author | Age | Files | Lines | |
|---|---|---|---|---|---|
| * | Change our simulator timing model to use continuous assignment guards. | Julian Blake Kongslie | 2021-04-05 | 1 | -13/+21 |
| | | | | | | | | Instead of depending on verilator getting $past right, this (ab-)uses the SystemVerilog scheduling model which allows us to get a consistent view of the universe by "isolating" the blocking updates. Easier to code to and seems to be more reliable in verilator. | ||||
| * | Yet another lame attempt. | Julian Blake Kongslie | 2021-03-28 | 1 | -12/+24 |
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| * | Use a separate memory module. | Julian Blake Kongslie | 2021-03-28 | 1 | -0/+30 |
| Hopefully this will infer a memory the way we want in Quartus. | |||||
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index : noncpu | |
| Unnamed repository; edit this file 'description' to name the repository. | Julian Blake Kongslie |
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