noncpu - Unnamed repository; edit this file 'description' to name the repository.

	Commit message (Collapse)	Author	Files	Lines
2021-04-05	Change our simulator timing model to use continuous assignment guards.	Julian Blake Kongslie	1	-50/+65
	Instead of depending on verilator getting $past right, this (ab-)uses the SystemVerilog scheduling model which allows us to get a consistent view of the universe by "isolating" the blocking updates. Easier to code to and seems to be more reliable in verilator.
2021-04-05	Make PC ADDR-sized rather than DATA-sized for now	Julian Blake Kongslie	1	-3/+3

2021-04-05	Remove some old debug messages.	Julian Blake Kongslie	1	-11/+1

2021-04-05	Longer runtime for verilator before giving up.	Julian Blake Kongslie	1	-1/+1

2021-04-05	Change build system so verilator doesn't require constant "make clean"s.	Julian Blake Kongslie	2	-3/+7

2021-04-04	Remove idx, add indirect jumps, renumber opcodes so NOP=0, add absolute ↵	Julian Blake Kongslie	3	-117/+133
	labels to asm.rb
2021-04-04	Add indirect memory operations.	Julian Blake Kongslie	3	-8/+34

2021-04-04	Very fancy improved Fibonacci machine, with HDL convert-to-ASCII functionality	Julian Blake Kongslie	3	-13/+80

2021-04-04	Remove unneeded .exe suffixes in bat scripts.	Julian Blake Kongslie	2	-4/+4

2021-04-04	Change assembler input to make it idempotent.	Julian Blake Kongslie	1	-0/+1

2021-03-30	Streamlined the Fibonacci program somewhat.	Julian Blake Kongslie	1	-17/+10

2021-03-29	Add a Fibonacci sequence to the end of output (no ASCII conversion yet)	Julian Blake Kongslie	2	-13/+20

2021-03-29	Trivial assembler.	Julian Blake Kongslie	2	-10/+71

2021-03-29	Trivial cleanup of initial memory image.	Julian Blake Kongslie	1	-2/+1

2021-03-29	Convert to using $sampled instead of $past, for more uniformity.	Julian Blake Kongslie	3	-13/+9

2021-03-29	Fix WIDTH warnings from verilator.	Julian Blake Kongslie	2	-6/+9

2021-03-28	Vastly improve the edit-rebuild-debug cycle.	Julian Blake Kongslie	1	-0/+7

2021-03-28	Possibly slightly less lame.	Julian Blake Kongslie	1	-10/+10

2021-03-28	Yet another lame attempt.	Julian Blake Kongslie	2	-34/+71

2021-03-28	Pessimize JTAG UART somewhat.	Julian Blake Kongslie	2	-8/+5

2021-03-28	Use a separate memory module.	Julian Blake Kongslie	2	-9/+110
	Hopefully this will infer a memory the way we want in Quartus.
2021-03-28	Some more interesting opcodes.	Julian Blake Kongslie	3	-24/+62