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* Add UART receive opbit.Julian Blake Kongslie2021-04-071-0/+12
* Switch back to $past-based scheduling; my clever idea wasn't clever enough.Julian Blake Kongslie2021-04-071-60/+45
* Change the null byte from no-op to halt.Julian Blake Kongslie2021-04-051-1/+1
* Change our simulator timing model to use continuous assignment guards.Julian Blake Kongslie2021-04-051-50/+65
* Make PC ADDR-sized rather than DATA-sized for nowJulian Blake Kongslie2021-04-051-3/+3
* Remove some old debug messages.Julian Blake Kongslie2021-04-051-11/+1
* Remove idx, add indirect jumps, renumber opcodes so NOP=0, add absolute label...Julian Blake Kongslie2021-04-041-31/+34
* Add indirect memory operations.Julian Blake Kongslie2021-04-041-6/+30
* Very fancy improved Fibonacci machine, with HDL convert-to-ASCII functionalityJulian Blake Kongslie2021-04-041-0/+11
* Add a Fibonacci sequence to the end of output (no ASCII conversion yet)Julian Blake Kongslie2021-03-291-1/+1
* Convert to using $sampled instead of $past, for more uniformity.Julian Blake Kongslie2021-03-291-8/+8
* Fix WIDTH warnings from verilator.Julian Blake Kongslie2021-03-291-5/+8
* Possibly slightly less lame.Julian Blake Kongslie2021-03-281-10/+10
* Yet another lame attempt.Julian Blake Kongslie2021-03-281-22/+47
* Pessimize JTAG UART somewhat.Julian Blake Kongslie2021-03-281-8/+1
* Use a separate memory module.Julian Blake Kongslie2021-03-281-9/+80
* Some more interesting opcodes.Julian Blake Kongslie2021-03-281-8/+23
* Initial commit.Julian Blake Kongslie2021-03-281-0/+89
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